Function assert_one

pulley/tests/all/interp.rs:29–71

(
    xs: impl IntoIterator<Item = (R0, V)>,
    op: impl Into<Op> + Debug,
    result: R1,
    expected: u64,
)

}

unsafe fn assert_one<R0, R1, V>(
    xs: impl IntoIterator<Item = (R0, V)>,
    op: impl Into<Op> + Debug,
    result: R1,
    expected: u64,
) where
    R0: Into<AnyReg>,
    R1: Into<AnyReg>,
    V: Into<Val>,
{
    eprintln!("=======================================================");
    let mut vm = Vm::new().unwrap();

    for (reg, val) in xs {
        let reg = reg.into();
        let val = val.into();
        eprintln!("{reg} = {val:#018x}");
        match (reg, val) {
            (AnyReg::X(r), Val::XReg(v)) => vm.state_mut()[r] = v,
            (AnyReg::F(r), Val::FReg(v)) => vm.state_mut()[r] = v,
            (AnyReg::V(_), Val::VReg(_)) => todo!(),
            (kind, val) => panic!("register kind and value mismatch: {kind:?} and {val:?}"),
        }
    }

    eprintln!("op = {op:?}");
    let op = op.into();

    unsafe {
        run(&mut vm, &[op, Op::Ret(Ret {})]).expect("should not trap");
    }

    eprintln!("expected = {expected:#018x}");

    let actual = match result.into() {
        AnyReg::X(r) => vm.state_mut()[r].get_u64(),
        AnyReg::F(r) => vm.state_mut()[r].get_f64().to_bits(),
        AnyReg::V(_) => todo!(),
    };
    eprintln!("actual   = {actual:#018x}");

    assert_eq!(expected, actual);
}

fn x(x: u8) -> XReg {
    XReg::new(x).unwrap()