Returns the Rust type used for the `IsleConstructorRaw` variants. RegMem operand types are width-tagged based on the DSL operand width (e.g. `rm8` → `GprMem8`, `xmm_m128` with `align` → `XmmMemAligned128`).
(op: &Operand)
| 23 | /// RegMem operand types are width-tagged based on the DSL operand width |
| 24 | /// (e.g. `rm8` → `GprMem8`, `xmm_m128` with `align` → `XmmMemAligned128`). |
| 25 | fn rust_param_raw(op: &Operand) -> String { |
| 26 | match op.location.kind() { |
| 27 | OperandKind::Imm(loc) => { |
| 28 | let bits = loc.bits(); |
| 29 | if op.extension.is_sign_extended() { |
| 30 | format!("i{bits}") |
| 31 | } else { |
| 32 | format!("u{bits}") |
| 33 | } |
| 34 | } |
| 35 | OperandKind::RegMem(rm) => { |
| 36 | let reg = rm.reg_class().unwrap(); |
| 37 | let aligned = if op.align { "Aligned" } else { "" }; |
| 38 | let bits = rm.bits(); |
| 39 | format!("&{reg}Mem{aligned}{bits}") |
| 40 | } |
| 41 | OperandKind::Mem(_) => { |
| 42 | format!("&SyntheticAmode") |
| 43 | } |
| 44 | OperandKind::Reg(r) | OperandKind::FixedReg(r) => r.reg_class().unwrap().to_string(), |
| 45 | } |
| 46 | } |
| 47 | |
| 48 | /// Returns the conversion function, if any, when converting the ISLE type for |
| 49 | /// this parameter to the assembler type for this parameter. Effectively |