Returns the type of this operand in ISLE as a part of the ISLE "raw" constructors. RegMem operand types are width-tagged based on the DSL operand width; see [`rust_param_raw`].
(op: &Operand)
| 250 | /// constructors. RegMem operand types are width-tagged based on the DSL |
| 251 | /// operand width; see [`rust_param_raw`]. |
| 252 | fn isle_param_raw(op: &Operand) -> String { |
| 253 | match op.location.kind() { |
| 254 | OperandKind::Imm(loc) => { |
| 255 | let bits = loc.bits(); |
| 256 | if op.extension.is_sign_extended() { |
| 257 | format!("i{bits}") |
| 258 | } else { |
| 259 | format!("u{bits}") |
| 260 | } |
| 261 | } |
| 262 | OperandKind::Reg(r) | OperandKind::FixedReg(r) => r.reg_class().unwrap().to_string(), |
| 263 | OperandKind::Mem(_) => { |
| 264 | if op.align { |
| 265 | unimplemented!("no way yet to mark an SyntheticAmode as aligned") |
| 266 | } else { |
| 267 | "SyntheticAmode".to_string() |
| 268 | } |
| 269 | } |
| 270 | OperandKind::RegMem(rm) => { |
| 271 | let reg = rm.reg_class().unwrap(); |
| 272 | let aligned = if op.align { "Aligned" } else { "" }; |
| 273 | let bits = rm.bits(); |
| 274 | format!("{reg}Mem{aligned}{bits}") |
| 275 | } |
| 276 | } |
| 277 | } |
| 278 | |
| 279 | /// Different kinds of ISLE constructors generated for a particular instruction. |
| 280 | /// |