Function isle_constructors

cranelift/codegen/meta/src/gen_asm.rs:404–502

Returns the ISLE constructors that are going to be used when generating this instruction. Note that one instruction might need multiple constructors, such as one for operating on memory and one for operating on registers.

(format: &Format)

/// Note that one instruction might need multiple constructors, such as one
/// for operating on memory and one for operating on registers.
fn isle_constructors(format: &Format) -> Vec<IsleConstructor> {
    use Mutability::*;
    use OperandKind::*;

    let write_operands = format
        .operands
        .iter()
        .filter(|o| o.mutability.is_write())
        .collect::<Vec<_>>();
    match &write_operands[..] {
        [] => {
            if format.eflags.is_write() {
                vec![IsleConstructor::ProducesFlagsSideEffect]
            } else {
                vec![IsleConstructor::NoReturnSideEffect]
            }
        }
        [one] => match one.mutability {
            Read => unreachable!(),
            ReadWrite | Write => match one.location.kind() {
                Imm(_) => unreachable!(),
                // One read/write register output? Output the instruction
                // and that register.
                Reg(r) | FixedReg(r) => match r.reg_class().unwrap() {
                    RegClass::Xmm => {
                        assert!(!format.eflags.is_read());
                        vec![IsleConstructor::RetXmm]
                    }
                    RegClass::Gpr => {
                        if format.eflags.is_read() {
                            vec![IsleConstructor::ConsumesFlagsReturnsGpr]
                        } else {
                            vec![IsleConstructor::RetGpr]
                        }
                    }
                },
                // One read/write memory operand? Output a side effect.
                Mem(_) => {
                    assert!(!format.eflags.is_read());
                    vec![IsleConstructor::RetMemorySideEffect]
                }
                // One read/write reg-mem output? We need constructors for
                // both variants.
                RegMem(rm) => match rm.reg_class().unwrap() {
                    RegClass::Xmm => {
                        assert!(!format.eflags.is_read());
                        vec![
                            IsleConstructor::RetXmm,
                            IsleConstructor::RetMemorySideEffect,
                        ]
                    }
                    RegClass::Gpr => {
                        if format.eflags.is_read() {
                            // FIXME: should expand this to include "consumes
                            // flags plus side effect" to model the
                            // memory-writing variant too. For example this
                            // means there's no memory-writing variant of
                            // `setcc` instructions generated.