| 30 | namespace subtle { |
| 31 | |
| 32 | inline void PauseCPU() { |
| 33 | #if defined(__x86_64__) |
| 34 | // Issue the x86 "pause" instruction, which tells the CPU that we |
| 35 | // are in a spinlock wait loop and should allow other hyperthreads |
| 36 | // to run, not speculate memory access, etc. |
| 37 | __asm__ __volatile__("pause" : : : "memory"); |
| 38 | #elif defined(__aarch64__) |
| 39 | // A "yield" instruction in aarch64 is essentially a nop, and does not cause |
| 40 | // enough delay to help backoff. "isb" is a barrier that, especially inside a |
| 41 | // loop, creates a small delay without consuming ALU resources. Experiments |
| 42 | // show that adding the isb instruction improves stability and reduces result |
| 43 | // jitter. Adding more delay than a single isb reduces performance. |
| 44 | __asm__ __volatile__("isb" : : : "memory"); |
| 45 | #else |
| 46 | // PauseCPU is not defined for other architectures. |
| 47 | #endif |
| 48 | } |
| 49 | |
| 50 | } // namespace subtle |
| 51 | } // namespace base |
no outgoing calls