* @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 * and PCLK1 prescalers. * @note This function should be used only after reset. * @param None * @retval None */
| 682 | * @retval None |
| 683 | */ |
| 684 | static void SetSysClockTo36(void) |
| 685 | { |
| 686 | __IO uint32_t StartUpCounter = 0, HSEStatus = 0; |
| 687 | |
| 688 | /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ |
| 689 | /* Enable HSE */ |
| 690 | RCC->CR |= ((uint32_t)RCC_CR_HSEON); |
| 691 | |
| 692 | /* Wait till HSE is ready and if Time out is reached exit */ |
| 693 | do |
| 694 | { |
| 695 | HSEStatus = RCC->CR & RCC_CR_HSERDY; |
| 696 | StartUpCounter++; |
| 697 | } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); |
| 698 | |
| 699 | if ((RCC->CR & RCC_CR_HSERDY) != RESET) |
| 700 | { |
| 701 | HSEStatus = (uint32_t)0x01; |
| 702 | } |
| 703 | else |
| 704 | { |
| 705 | HSEStatus = (uint32_t)0x00; |
| 706 | } |
| 707 | |
| 708 | if (HSEStatus == (uint32_t)0x01) |
| 709 | { |
| 710 | /* Enable Prefetch Buffer */ |
| 711 | FLASH->ACR |= FLASH_ACR_PRFTBE; |
| 712 | |
| 713 | /* Flash 1 wait state */ |
| 714 | FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); |
| 715 | FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; |
| 716 | |
| 717 | /* HCLK = SYSCLK */ |
| 718 | RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; |
| 719 | |
| 720 | /* PCLK2 = HCLK */ |
| 721 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; |
| 722 | |
| 723 | /* PCLK1 = HCLK */ |
| 724 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; |
| 725 | |
| 726 | #ifdef STM32F10X_CL |
| 727 | /* Configure PLLs ------------------------------------------------------*/ |
| 728 | |
| 729 | /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ |
| 730 | RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); |
| 731 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | |
| 732 | RCC_CFGR_PLLMULL9); |
| 733 | |
| 734 | /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ |
| 735 | /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ |
| 736 | |
| 737 | RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | |
| 738 | RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); |
| 739 | RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | |
| 740 | RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); |
| 741 |