* @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 * and PCLK1 prescalers. * @note This function should be used only after reset. * @param None * @retval None */
| 578 | * @retval None |
| 579 | */ |
| 580 | static void SetSysClockTo24(void) |
| 581 | { |
| 582 | __IO uint32_t StartUpCounter = 0, HSEStatus = 0; |
| 583 | |
| 584 | /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ |
| 585 | /* Enable HSE */ |
| 586 | RCC->CR |= ((uint32_t)RCC_CR_HSEON); |
| 587 | |
| 588 | /* Wait till HSE is ready and if Time out is reached exit */ |
| 589 | do |
| 590 | { |
| 591 | HSEStatus = RCC->CR & RCC_CR_HSERDY; |
| 592 | StartUpCounter++; |
| 593 | } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); |
| 594 | |
| 595 | if ((RCC->CR & RCC_CR_HSERDY) != RESET) |
| 596 | { |
| 597 | HSEStatus = (uint32_t)0x01; |
| 598 | } |
| 599 | else |
| 600 | { |
| 601 | HSEStatus = (uint32_t)0x00; |
| 602 | } |
| 603 | |
| 604 | if (HSEStatus == (uint32_t)0x01) |
| 605 | { |
| 606 | #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL |
| 607 | /* Enable Prefetch Buffer */ |
| 608 | FLASH->ACR |= FLASH_ACR_PRFTBE; |
| 609 | |
| 610 | /* Flash 0 wait state */ |
| 611 | FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); |
| 612 | FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; |
| 613 | #endif |
| 614 | |
| 615 | /* HCLK = SYSCLK */ |
| 616 | RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; |
| 617 | |
| 618 | /* PCLK2 = HCLK */ |
| 619 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; |
| 620 | |
| 621 | /* PCLK1 = HCLK */ |
| 622 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; |
| 623 | |
| 624 | #ifdef STM32F10X_CL |
| 625 | /* Configure PLLs ------------------------------------------------------*/ |
| 626 | /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ |
| 627 | RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); |
| 628 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | |
| 629 | RCC_CFGR_PLLMULL6); |
| 630 | |
| 631 | /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ |
| 632 | /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ |
| 633 | RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | |
| 634 | RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); |
| 635 | RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | |
| 636 | RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); |
| 637 |