* @brief Configures the System clock frequency, AHB/APBx prescalers and Flash * settings. * @note This function should be called only once the RCC clock configuration * is reset to the default reset state (done in SystemInit() function). * @param None * @retval None */
| 269 | * @retval None |
| 270 | */ |
| 271 | static void SetSysClock(void) |
| 272 | { |
| 273 | /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/ |
| 274 | #if defined (PLL_SOURCE_HSI) |
| 275 | |
| 276 | /* At this stage the HSI is already enabled */ |
| 277 | |
| 278 | /* Enable Prefetch Buffer and set Flash Latency */ |
| 279 | FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY; |
| 280 | |
| 281 | /* HCLK = SYSCLK */ |
| 282 | RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; |
| 283 | |
| 284 | /* PCLK = HCLK */ |
| 285 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1; |
| 286 | |
| 287 | /* PLL configuration = (HSI/2) * 12 = ~48 MHz */ |
| 288 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); |
| 289 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_Div2 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL12); |
| 290 | |
| 291 | /* Enable PLL */ |
| 292 | RCC->CR |= RCC_CR_PLLON; |
| 293 | |
| 294 | /* Wait till PLL is ready */ |
| 295 | while((RCC->CR & RCC_CR_PLLRDY) == 0) |
| 296 | { |
| 297 | } |
| 298 | |
| 299 | /* Select PLL as system clock source */ |
| 300 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); |
| 301 | RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; |
| 302 | |
| 303 | /* Wait till PLL is used as system clock source */ |
| 304 | while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL) |
| 305 | { |
| 306 | } |
| 307 | #else |
| 308 | |
| 309 | __IO uint32_t StartUpCounter = 0, HSEStatus = 0; |
| 310 | |
| 311 | #if defined (PLL_SOURCE_HSE) |
| 312 | /* Enable HSE */ |
| 313 | RCC->CR |= ((uint32_t)RCC_CR_HSEON); |
| 314 | #elif defined (PLL_SOURCE_HSE_BYPASS) |
| 315 | /* HSE oscillator bypassed with external clock */ |
| 316 | RCC->CR |= (uint32_t)(RCC_CR_HSEON | RCC_CR_HSEBYP); |
| 317 | #endif /* PLL_SOURCE_HSE */ |
| 318 | |
| 319 | /* Wait till HSE is ready and if Time out is reached exit */ |
| 320 | do |
| 321 | { |
| 322 | HSEStatus = RCC->CR & RCC_CR_HSERDY; |
| 323 | StartUpCounter++; |
| 324 | } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); |
| 325 | |
| 326 | if ((RCC->CR & RCC_CR_HSERDY) != RESET) |
| 327 | { |
| 328 | HSEStatus = (uint32_t)0x01; |