| 176 | } TLBEntry; |
| 177 | |
| 178 | struct RISCVCPUState { |
| 179 | RISCVCPUCommonState common; /* must be first */ |
| 180 | |
| 181 | target_ulong pc; |
| 182 | target_ulong reg[32]; |
| 183 | |
| 184 | #ifdef USE_GLOBAL_VARIABLES |
| 185 | /* faster to use global variables with emscripten */ |
| 186 | uint8_t *__code_ptr, *__code_end; |
| 187 | target_ulong __code_to_pc_addend; |
| 188 | #endif |
| 189 | |
| 190 | #if FLEN > 0 |
| 191 | fp_uint fp_reg[32]; |
| 192 | uint32_t fflags; |
| 193 | uint8_t frm; |
| 194 | #endif |
| 195 | |
| 196 | uint8_t cur_xlen; /* current XLEN value, <= MAX_XLEN */ |
| 197 | uint8_t priv; /* see PRV_x */ |
| 198 | uint8_t fs; /* MSTATUS_FS value */ |
| 199 | uint8_t mxl; /* MXL field in MISA register */ |
| 200 | |
| 201 | int32_t n_cycles; /* only used inside the CPU loop */ |
| 202 | uint64_t insn_counter; |
| 203 | BOOL power_down_flag; |
| 204 | int pending_exception; /* used during MMU exception handling */ |
| 205 | target_ulong pending_tval; |
| 206 | |
| 207 | /* CSRs */ |
| 208 | target_ulong mstatus; |
| 209 | target_ulong mtvec; |
| 210 | target_ulong mscratch; |
| 211 | target_ulong mepc; |
| 212 | target_ulong mcause; |
| 213 | target_ulong mtval; |
| 214 | target_ulong mhartid; /* ro */ |
| 215 | uint32_t misa; |
| 216 | uint32_t mie; |
| 217 | uint32_t mip; |
| 218 | uint32_t medeleg; |
| 219 | uint32_t mideleg; |
| 220 | uint32_t mcounteren; |
| 221 | |
| 222 | target_ulong stvec; |
| 223 | target_ulong sscratch; |
| 224 | target_ulong sepc; |
| 225 | target_ulong scause; |
| 226 | target_ulong stval; |
| 227 | #if MAX_XLEN == 32 |
| 228 | uint32_t satp; |
| 229 | #else |
| 230 | uint64_t satp; /* currently 64 bit physical addresses max */ |
| 231 | #endif |
| 232 | uint32_t scounteren; |
| 233 | |
| 234 | target_ulong load_res; /* for atomic LR/SC */ |
| 235 |
nothing calls this directly
no outgoing calls
no test coverage detected