Code
Hub
Workspaces
Following
Trending
Connect
MCP
copy
Create free account
hub
/
github.com/a16z/jolt
/ functions
Functions
2,242 in github.com/a16z/jolt
⨍
Functions
2,242
◇
Types & classes
398
Method
evaluate_mle
(&self, r: &[F])
jolt-core/src/zkvm/lookup_table/upper_word.rs:17
Method
evaluate_mle
(&self, r: &[F])
jolt-core/src/zkvm/lookup_table/unsigned_less_than_equal.rs:18
Method
evaluate_mle
(&self, r: &[F])
jolt-core/src/zkvm/lookup_table/shift_right_bitmask.rs:23
Method
evaluate_mle
(&self, r: &[F])
jolt-core/src/zkvm/lookup_table/valid_signed_remainder.rs:51
Method
evaluate_mle
(&self, r: &[F])
jolt-core/src/zkvm/lookup_table/virtual_rotr.rs:34
Method
evaluate_mle
(&self, r: &[F])
jolt-core/src/zkvm/lookup_table/halfword_alignment.rs:19
Method
evaluate_mle
(&self, r: &[F])
jolt-core/src/zkvm/lookup_table/unsigned_less_than.rs:19
Method
evaluate_mle
(&self, r: &[F])
jolt-core/src/zkvm/lookup_table/movsign.rs:22
Method
evaluate_mle
(&self, r: &[F])
jolt-core/src/zkvm/lookup_table/pow2.rs:19
Method
evaluate_mle
(&self, r: &[F])
jolt-core/src/zkvm/lookup_table/not_equal.rs:24
Method
evaluate_mle
(&self, r: &[F])
jolt-core/src/zkvm/lookup_table/or.rs:19
Method
evaluate_mle
(&self, r: &[F])
jolt-core/src/zkvm/lookup_table/signed_less_than.rs:23
Method
evaluate_mle
(&self, r: &[F])
jolt-core/src/zkvm/lookup_table/valid_div0.rs:27
Method
evaluate_mle
(&self, r: &[F])
jolt-core/src/zkvm/lookup_table/and.rs:19
Function
evaluate_test
()
jolt-core/src/poly/one_hot_polynomial.rs:615
Function
evaluation
()
jolt-core/src/poly/dense_mlpoly.rs:462
Method
evaluation_openings_mut
(&mut self)
jolt-core/src/poly/opening_proof.rs:608
Function
exception
()
tracer/src/emulator/cpu.rs:1914
Method
exec
(&self, cpu: &mut Cpu, ram_access: &mut <AMOMINUW as RISCVInstruction>::RAMAccess)
tracer/src/instruction/amominuw.rs:19
Method
exec
(&self, cpu: &mut Cpu, ram_access: &mut <SD as RISCVInstruction>::RAMAccess)
tracer/src/instruction/sd.rs:21
Method
exec
(&self, cpu: &mut Cpu, _: &mut <REMUW as RISCVInstruction>::RAMAccess)
tracer/src/instruction/remuw.rs:17
Method
exec
(&self, cpu: &mut Cpu, ram_access: &mut <AMOMIND as RISCVInstruction>::RAMAccess)
tracer/src/instruction/amomind.rs:19
Method
exec
(&self, cpu: &mut Cpu, _: &mut <SRAIW as RISCVInstruction>::RAMAccess)
tracer/src/instruction/sraiw.rs:17
Method
exec
(&self, cpu: &mut Cpu, ram_access: &mut <LHU as RISCVInstruction>::RAMAccess)
tracer/src/instruction/lhu.rs:34
Method
exec
(&self, cpu: &mut Cpu, _: &mut <ANDI as RISCVInstruction>::RAMAccess)
tracer/src/instruction/andi.rs:19
Method
exec
(&self, cpu: &mut Cpu, _: &mut <VirtualAssertEQ as RISCVInstruction>::RAMAccess)
tracer/src/instruction/virtual_assert_eq.rs:20
Method
exec
(&self, cpu: &mut Cpu, _: &mut <VirtualMovsign as RISCVInstruction>::RAMAccess)
tracer/src/instruction/virtual_movsign.rs:29
Method
exec
(&self, cpu: &mut Cpu, _: &mut <SLTIU as RISCVInstruction>::RAMAccess)
tracer/src/instruction/sltiu.rs:19
Method
exec
(&self, cpu: &mut Cpu, _: &mut <MULHSU as RISCVInstruction>::RAMAccess)
tracer/src/instruction/mulhsu.rs:27
Method
exec
(&self, cpu: &mut Cpu, _: &mut <SRLI as RISCVInstruction>::RAMAccess)
tracer/src/instruction/srli.rs:25
Method
exec
(&self, cpu: &mut Cpu, _: &mut <VirtualSRL as RISCVInstruction>::RAMAccess)
tracer/src/instruction/virtual_srl.rs:20
Method
exec
(&self, cpu: &mut Cpu, _: &mut <BGE as RISCVInstruction>::RAMAccess)
tracer/src/instruction/bge.rs:19
Method
exec
(&self, cpu: &mut Cpu, _: &mut <SRL as RISCVInstruction>::RAMAccess)
tracer/src/instruction/srl.rs:28
Method
exec
(&self, cpu: &mut Cpu, _: &mut <AUIPC as RISCVInstruction>::RAMAccess)
tracer/src/instruction/auipc.rs:19
Method
exec
(&self, cpu: &mut Cpu, _: &mut <SLLIW as RISCVInstruction>::RAMAccess)
tracer/src/instruction/slliw.rs:17
Method
exec
(&self, cpu: &mut Cpu, ram_access: &mut <AMOORD as RISCVInstruction>::RAMAccess)
tracer/src/instruction/amoord.rs:19
Method
exec
(&self, cpu: &mut Cpu, _: &mut <VirtualSRAI as RISCVInstruction>::RAMAccess)
tracer/src/instruction/virtual_srai.rs:20
Method
exec
(&self, cpu: &mut Cpu, ram_access: &mut <AMOMAXUD as RISCVInstruction>::RAMAccess)
tracer/src/instruction/amomaxud.rs:19
Method
exec
(&self, cpu: &mut Cpu, ram_access: &mut <AMOMAXUW as RISCVInstruction>::RAMAccess)
tracer/src/instruction/amomaxuw.rs:19
Method
exec
(&self, cpu: &mut Cpu, _: &mut <VirtualMULI as RISCVInstruction>::RAMAccess)
tracer/src/instruction/virtual_muli.rs:22
Method
exec
(&self, _: &mut Cpu, _: &mut <FENCE as RISCVInstruction>::RAMAccess)
tracer/src/instruction/fence.rs:19
Method
exec
(&self, cpu: &mut Cpu, _: &mut <ADDW as RISCVInstruction>::RAMAccess)
tracer/src/instruction/addw.rs:19
Method
exec
(&self, cpu: &mut Cpu, _: &mut <SRAW as RISCVInstruction>::RAMAccess)
tracer/src/instruction/sraw.rs:17
Method
exec
(&self, cpu: &mut Cpu, ram_access: &mut <LWU as RISCVInstruction>::RAMAccess)
tracer/src/instruction/lwu.rs:17
Method
exec
(&self, cpu: &mut Cpu, ram_access: &mut <AMOADDW as RISCVInstruction>::RAMAccess)
tracer/src/instruction/amoaddw.rs:19
Method
exec
(&self, cpu: &mut Cpu, _: &mut <XOR as RISCVInstruction>::RAMAccess)
tracer/src/instruction/xor.rs:19
Method
exec
(&self, cpu: &mut Cpu, ram_access: &mut <LD as RISCVInstruction>::RAMAccess)
tracer/src/instruction/ld.rs:17
Method
exec
(&self, cpu: &mut Cpu, _: &mut <VirtualAssertLTE as RISCVInstruction>::RAMAccess)
tracer/src/instruction/virtual_assert_lte.rs:20
Method
exec
( &self, cpu: &mut Cpu, _: &mut <VirtualShiftRightBitmaskI as RISCVInstruction>::RAMAc
tracer/src/instruction/virtual_shift_right_bitmaski.rs:23
Method
exec
(&self, cpu: &mut Cpu, _: &mut <SLL as RISCVInstruction>::RAMAccess)
tracer/src/instruction/sll.rs:25
Method
exec
(&self, cpu: &mut Cpu, _: &mut <VirtualPow2 as RISCVInstruction>::RAMAccess)
tracer/src/instruction/virtual_pow2.rs:23
Method
exec
(&self, cpu: &mut Cpu, ram_access: &mut <SH as RISCVInstruction>::RAMAccess)
tracer/src/instruction/sh.rs:39
Method
exec
(&self, cpu: &mut Cpu, _: &mut <BGEU as RISCVInstruction>::RAMAccess)
tracer/src/instruction/bgeu.rs:19
Method
exec
(&self, cpu: &mut Cpu, ram_access: &mut <AMOSWAPD as RISCVInstruction>::RAMAccess)
tracer/src/instruction/amoswapd.rs:19
Method
exec
(&self, cpu: &mut Cpu, ram_access: &mut <SW as RISCVInstruction>::RAMAccess)
tracer/src/instruction/sw.rs:21
Method
exec
(&self, cpu: &mut Cpu, _: &mut <DIVUW as RISCVInstruction>::RAMAccess)
tracer/src/instruction/divuw.rs:17
Method
exec
(&self, cpu: &mut Cpu, _: &mut <LUI as RISCVInstruction>::RAMAccess)
tracer/src/instruction/lui.rs:19
Method
exec
(&self, cpu: &mut Cpu, ram_access: &mut <LW as RISCVInstruction>::RAMAccess)
tracer/src/instruction/lw.rs:21
Method
exec
(&self, cpu: &mut Cpu, ram_access: &mut <AMOMAXW as RISCVInstruction>::RAMAccess)
tracer/src/instruction/amomaxw.rs:19
Method
exec
(&self, cpu: &mut Cpu, _: &mut <DIV as RISCVInstruction>::RAMAccess)
tracer/src/instruction/div.rs:33
Method
exec
(&self, cpu: &mut Cpu, _: &mut <BLT as RISCVInstruction>::RAMAccess)
tracer/src/instruction/blt.rs:19
Method
exec
(&self, cpu: &mut Cpu, _: &mut <SUBW as RISCVInstruction>::RAMAccess)
tracer/src/instruction/subw.rs:17
Method
exec
(&self, cpu: &mut Cpu, _: &mut <VirtualSRA as RISCVInstruction>::RAMAccess)
tracer/src/instruction/virtual_sra.rs:20
Method
exec
(&self, cpu: &mut Cpu, ram_access: &mut <LB as RISCVInstruction>::RAMAccess)
tracer/src/instruction/lb.rs:31
Method
exec
(&self, cpu: &mut Cpu, ram_access: &mut <AMOXORW as RISCVInstruction>::RAMAccess)
tracer/src/instruction/amoxorw.rs:19
Method
exec
( &self, cpu: &mut Cpu, _: &mut <VirtualAssertHalfwordAlignment as RISCVInstruction>::
tracer/src/instruction/virtual_assert_halfword_alignment.rs:20
Method
exec
(&self, cpu: &mut Cpu, _: &mut <MULW as RISCVInstruction>::RAMAccess)
tracer/src/instruction/mulw.rs:17
Method
exec
(&self, cpu: &mut Cpu, ram_access: &mut <AMOANDW as RISCVInstruction>::RAMAccess)
tracer/src/instruction/amoandw.rs:19
Method
exec
(&self, cpu: &mut Cpu, _: &mut <ADD as RISCVInstruction>::RAMAccess)
tracer/src/instruction/add.rs:19
Method
exec
(&self, cpu: &mut Cpu, ram_access: &mut <AMOADDD as RISCVInstruction>::RAMAccess)
tracer/src/instruction/amoaddd.rs:19
Method
exec
(&self, cpu: &mut Cpu, _: &mut <SLTI as RISCVInstruction>::RAMAccess)
tracer/src/instruction/slti.rs:19
Method
exec
(&self, cpu: &mut Cpu, _: &mut <VirtualAssertValidDiv0 as RISCVInstruction>::RAMAccess)
tracer/src/instruction/virtual_assert_valid_div0.rs:23
Method
exec
(&self, cpu: &mut Cpu, _: &mut <DIVU as RISCVInstruction>::RAMAccess)
tracer/src/instruction/divu.rs:33
Method
exec
(&self, cpu: &mut Cpu, _: &mut <SUB as RISCVInstruction>::RAMAccess)
tracer/src/instruction/sub.rs:19
Method
exec
(&self, cpu: &mut Cpu, _: &mut <SRLIW as RISCVInstruction>::RAMAccess)
tracer/src/instruction/srliw.rs:17
Method
exec
(&self, cpu: &mut Cpu, _: &mut <SRA as RISCVInstruction>::RAMAccess)
tracer/src/instruction/sra.rs:28
Method
exec
(&self, cpu: &mut Cpu, _: &mut <JAL as RISCVInstruction>::RAMAccess)
tracer/src/instruction/jal.rs:19
Method
exec
(&self, cpu: &mut Cpu, _: &mut <DIVW as RISCVInstruction>::RAMAccess)
tracer/src/instruction/divw.rs:17
Method
exec
( &self, cpu: &mut Cpu, _: &mut <VirtualShiftRightBitmask as RISCVInstruction>::RAMAcc
tracer/src/instruction/virtual_shift_right_bitmask.rs:23
Method
exec
(&self, cpu: &mut Cpu, _: &mut <ORI as RISCVInstruction>::RAMAccess)
tracer/src/instruction/ori.rs:19
Method
exec
(&self, cpu: &mut Cpu, ram_access: &mut <AMOXORD as RISCVInstruction>::RAMAccess)
tracer/src/instruction/amoxord.rs:19
Method
exec
(&self, cpu: &mut Cpu, _: &mut <ADDIW as RISCVInstruction>::RAMAccess)
tracer/src/instruction/addiw.rs:19
Method
exec
(&self, cpu: &mut Cpu, ram_access: &mut <AMOORW as RISCVInstruction>::RAMAccess)
tracer/src/instruction/amoorw.rs:19
Method
exec
(&self, cpu: &mut Cpu, _: &mut <BNE as RISCVInstruction>::RAMAccess)
tracer/src/instruction/bne.rs:19
Method
exec
(&self, cpu: &mut Cpu, ram_access: &mut <AMOMAXD as RISCVInstruction>::RAMAccess)
tracer/src/instruction/amomaxd.rs:19
Method
exec
(&self, cpu: &mut Cpu, _: &mut <MUL as RISCVInstruction>::RAMAccess)
tracer/src/instruction/mul.rs:19
Method
exec
(&self, cpu: &mut Cpu, ram_access: &mut <SCW as RISCVInstruction>::RAMAccess)
tracer/src/instruction/scw.rs:19
Method
exec
(&self, cpu: &mut Cpu, ram_access: &mut <AMOANDD as RISCVInstruction>::RAMAccess)
tracer/src/instruction/amoandd.rs:19
Method
exec
(&self, cpu: &mut Cpu, _: &mut <SLLI as RISCVInstruction>::RAMAccess)
tracer/src/instruction/slli.rs:23
Method
exec
(&self, cpu: &mut Cpu, _: &mut <XORI as RISCVInstruction>::RAMAccess)
tracer/src/instruction/xori.rs:19
Method
exec
(&self, cpu: &mut Cpu, _: &mut <REM as RISCVInstruction>::RAMAccess)
tracer/src/instruction/rem.rs:32
Method
exec
(&self, cpu: &mut Cpu, _: &mut <SLT as RISCVInstruction>::RAMAccess)
tracer/src/instruction/slt.rs:19
Method
exec
(&self, cpu: &mut Cpu, _: &mut <SLLW as RISCVInstruction>::RAMAccess)
tracer/src/instruction/sllw.rs:17
Method
exec
(&self, cpu: &mut Cpu, _: &mut <REMU as RISCVInstruction>::RAMAccess)
tracer/src/instruction/remu.rs:33
Method
exec
(&self, cpu: &mut Cpu, _: &mut <VirtualROTRI as RISCVInstruction>::RAMAccess)
tracer/src/instruction/virtual_rotri.rs:18
Method
exec
(&self, cpu: &mut Cpu, _: &mut <VirtualPow2I as RISCVInstruction>::RAMAccess)
tracer/src/instruction/virtual_pow2i.rs:23
Method
exec
(&self, cpu: &mut Cpu, _: &mut <BEQ as RISCVInstruction>::RAMAccess)
tracer/src/instruction/beq.rs:19
Method
exec
(&self, cpu: &mut Cpu, ram_access: &mut <AMOMINUD as RISCVInstruction>::RAMAccess)
tracer/src/instruction/amominud.rs:19
Method
exec
(&self, cpu: &mut Cpu, _: &mut <REMW as RISCVInstruction>::RAMAccess)
tracer/src/instruction/remw.rs:17
Method
exec
No architectural effects Signals to emulator to record cycles through early exit of trap
tracer/src/instruction/ecall.rs:27
← previous
next →
1,001–1,100 of 2,242, ranked by callers