helper function for creating RTLIL code for binary operations

create RTLIL from an AST node all generated cells, wires and processes are added to the module pointed to by 'current_module' when the AST node is an

XXX(aki): this is a lazy way to do this i know,,,

Get the state of bit bi, which has value 2^bi. Bits beyond the * number's length are considered to be 0. */

Has the signal a known constant value in the initial state? For sync-only FFs outputs, this is their initval. For logic loops, multiple drivers or un

Use these private utilities instead

Append all wires to a SigSpec

Operations with run-time parameters (offsets, amounts, etc). These operations are used for computations.

Evidently the compiler wants BigUnsigned:: on the return type because, at * that point, it hasn't yet parsed the BigUnsigned:: on the name to get the

Duplicatation (preferred instead):

delete all children in this node

Set Operations