| 477 | opcode_info_map[obj_module_opcode.op_code]=obj_module_opcode; |
| 478 | } |
| 479 | void update_pooling_module_opcode_table(Opcode_info & obj_module_opcode,map<opcode_num_e, Opcode_info> & opcode_info_map,int batch_size){ |
| 480 | |
| 481 | Module_info module_default; |
| 482 | module_default.module_target_info = FPGA; |
| 483 | module_default.module_type = HW_POOL; |
| 484 | module_default.module_name = "Pooling"; /// TODO abid needs to update the layer information based on the enum instead of layer name |
| 485 | module_default.num_total_ports=11; // TODO need to check with buffer management & init module |
| 486 | obj_module_opcode.mega_module = module_default; |
| 487 | |
| 488 | /*** pooling mega module ports & these port order should be same as deploy file *********/ |
| 489 | |
| 490 | Port_info port_defualt; |
| 491 | port_defualt.data_type = XI_INT8; |
| 492 | port_defualt.size_datatype = XI_INT8_S; |
| 493 | port_defualt.memory_align_required=32; // TODO need to check with buffer management & init module |
| 494 | port_defualt.memory_map_info = __SDS_NON_CACHEABLE; |
| 495 | port_defualt.port_enum=XI_INPUT; |
| 496 | port_defualt.port_width=XI_128BIT_WIDTH; |
| 497 | port_defualt.qant_scheme_type = g_quant_value; |
| 498 | packinfo input_pack; |
| 499 | |
| 500 | input_pack.dim = XI_CHANNEL; |
| 501 | input_pack.mem_contiguous = true; |
| 502 | input_pack.mod_div_factor = (port_defualt.port_width/port_defualt.size_datatype)/batch_size; |
| 503 | input_pack.sep=XI_DIVISION; |
| 504 | |
| 505 | port_defualt.pack_info_vec.push_back(input_pack); |
| 506 | |
| 507 | input_pack.dim = XI_HEIGHT; |
| 508 | input_pack.mem_contiguous = true; |
| 509 | input_pack.mod_div_factor = 0; |
| 510 | input_pack.sep=XI_NONE; |
| 511 | |
| 512 | port_defualt.pack_info_vec.push_back(input_pack); |
| 513 | |
| 514 | input_pack.dim = XI_WIDTH; |
| 515 | input_pack.mem_contiguous = true; |
| 516 | input_pack.mod_div_factor = 0; |
| 517 | input_pack.sep=XI_NONE; |
| 518 | |
| 519 | port_defualt.pack_info_vec.push_back(input_pack); |
| 520 | input_pack.dim = XI_INTERLEAVED; |
| 521 | input_pack.mem_contiguous = true; |
| 522 | input_pack.mod_div_factor = (port_defualt.port_width/port_defualt.size_datatype)/batch_size; |
| 523 | input_pack.sep=XI_MODULO; |
| 524 | |
| 525 | port_defualt.pack_info_vec.push_back(input_pack); |
| 526 | |
| 527 | input_pack.dim = XI_BATCH; |
| 528 | input_pack.mem_contiguous = true; |
| 529 | input_pack.mod_div_factor = 0; |
| 530 | input_pack.sep=XI_NONE; |
| 531 | |
| 532 | port_defualt.pack_info_vec.push_back(input_pack); |
| 533 | |
| 534 | obj_module_opcode.port_vec.push_back(port_defualt); |
| 535 | |
| 536 | Port_info port_defualt1; |