| 233 | |
| 234 | } |
| 235 | void update_fc_module_opcode_table(Opcode_info & obj_module_opcode,map<opcode_num_e, Opcode_info> & opcode_info_map,int batch_size){ |
| 236 | |
| 237 | Module_info module_default; |
| 238 | #if FC_KERNEL_EXIST |
| 239 | module_default.module_target_info = FPGA; |
| 240 | module_default.module_type = HW_FC; |
| 241 | #else |
| 242 | module_default.module_target_info = CPU; |
| 243 | module_default.module_type = SW_FC; |
| 244 | #endif |
| 245 | |
| 246 | module_default.module_name = "InnerProduct"; /// TODO abid needs to update the layer information based on the enum instead of layer name |
| 247 | module_default.num_total_ports=11; // TODO need to check with buffer management & init module |
| 248 | obj_module_opcode.mega_module = module_default; |
| 249 | |
| 250 | /*** fc mega module ports & these port order should be same as deploy file*********/ |
| 251 | |
| 252 | Port_info port_defualt; |
| 253 | |
| 254 | #if FC_KERNEL_EXIST |
| 255 | port_defualt.data_type = XI_INT8; |
| 256 | port_defualt.size_datatype = XI_INT8_S; |
| 257 | port_defualt.port_width=XI_128BIT_WIDTH; |
| 258 | port_defualt.memory_align_required=32; // TODO need to check with buffer management & init module |
| 259 | port_defualt.memory_map_info = __SDS_NON_CACHEABLE; |
| 260 | port_defualt.port_enum=XI_INPUT; |
| 261 | port_defualt.qant_scheme_type = QUNT_FIXED; |
| 262 | #else |
| 263 | port_defualt.data_type = XI_FLOAT; |
| 264 | port_defualt.size_datatype = XI_FLOAT_S; |
| 265 | port_defualt.port_width=XI_32BIT_WIDTH; |
| 266 | port_defualt.memory_align_required=32; // TODO need to check with buffer management & init module |
| 267 | port_defualt.memory_map_info = __MALLOC_TYPE; |
| 268 | port_defualt.port_enum=XI_INPUT; |
| 269 | port_defualt.qant_scheme_type = g_quant_value; |
| 270 | #endif |
| 271 | |
| 272 | packinfo input_pack; |
| 273 | |
| 274 | input_pack.dim = XI_CHANNEL; |
| 275 | input_pack.mem_contiguous = true; |
| 276 | input_pack.mod_div_factor = 0; |
| 277 | input_pack.sep=XI_NONE; |
| 278 | |
| 279 | port_defualt.pack_info_vec.push_back(input_pack); |
| 280 | |
| 281 | input_pack.dim = XI_HEIGHT; |
| 282 | input_pack.mem_contiguous = true; |
| 283 | input_pack.mod_div_factor = 0; |
| 284 | input_pack.sep=XI_NONE; |
| 285 | port_defualt.pack_info_vec.push_back(input_pack); |
| 286 | |
| 287 | input_pack.dim = XI_WIDTH; |
| 288 | input_pack.mem_contiguous = true; |
| 289 | input_pack.mod_div_factor = 0; |
| 290 | input_pack.sep=XI_NONE; |
| 291 | |
| 292 | port_defualt.pack_info_vec.push_back(input_pack); |