| 369 | |
| 370 | } |
| 371 | void update_deconv_module_opcode_table(Opcode_info & obj_module_opcode,map<opcode_num_e, Opcode_info> & opcode_info_map,int batch_size){ |
| 372 | |
| 373 | Module_info module_default; |
| 374 | module_default.module_target_info = FPGA; |
| 375 | module_default.module_type = HW_DECONV; |
| 376 | module_default.module_name = "Deconvolution"; /// TODO abid needs to update the layer information based on the enum instead of layer name |
| 377 | module_default.num_total_ports=11; // TODO need to check with buffer management & init module |
| 378 | obj_module_opcode.mega_module = module_default; |
| 379 | |
| 380 | /*** deconv mega module ports & these port order should be same as deploy file *********/ |
| 381 | |
| 382 | Port_info port_defualt; |
| 383 | port_defualt.port_width=XI_16BIT_WIDTH; |
| 384 | port_defualt.data_type = XI_INT16; |
| 385 | port_defualt.size_datatype = XI_INT16_S; |
| 386 | port_defualt.memory_align_required=32; // TODO need to check with buffer management & init module |
| 387 | port_defualt.memory_map_info = __SDS_NON_CACHEABLE; |
| 388 | port_defualt.port_enum=XI_INPUT; |
| 389 | port_defualt.qant_scheme_type = g_quant_value; |
| 390 | packinfo input_pack; |
| 391 | |
| 392 | input_pack.dim = XI_CHANNEL; |
| 393 | input_pack.mem_contiguous = true; |
| 394 | input_pack.mod_div_factor = 0; |
| 395 | input_pack.sep=XI_NONE; |
| 396 | |
| 397 | port_defualt.pack_info_vec.push_back(input_pack); |
| 398 | |
| 399 | |
| 400 | input_pack.dim = XI_HEIGHT; |
| 401 | input_pack.mem_contiguous = true; |
| 402 | input_pack.mod_div_factor = 0; |
| 403 | input_pack.sep=XI_NONE; |
| 404 | port_defualt.pack_info_vec.push_back(input_pack); |
| 405 | |
| 406 | input_pack.dim = XI_WIDTH; |
| 407 | input_pack.mem_contiguous = true; |
| 408 | input_pack.mod_div_factor = 0; |
| 409 | input_pack.sep=XI_NONE; |
| 410 | |
| 411 | port_defualt.pack_info_vec.push_back(input_pack); |
| 412 | |
| 413 | input_pack.dim = XI_INTERLEAVED; |
| 414 | input_pack.mem_contiguous = true; |
| 415 | input_pack.mod_div_factor = 0; |
| 416 | input_pack.sep=XI_NONE; |
| 417 | |
| 418 | port_defualt.pack_info_vec.push_back(input_pack); |
| 419 | |
| 420 | input_pack.dim = XI_BATCH; |
| 421 | input_pack.mem_contiguous = true; |
| 422 | input_pack.mod_div_factor = 0; |
| 423 | input_pack.sep=XI_NONE; |
| 424 | |
| 425 | port_defualt.pack_info_vec.push_back(input_pack); |
| 426 | |
| 427 | obj_module_opcode.port_vec.push_back(port_defualt); |
| 428 | |