| 35 | _quant_scheme_e g_quant_value; |
| 36 | |
| 37 | void update_conv_module_opcode_table(Opcode_info & obj_module_opcode,map<opcode_num_e, Opcode_info> & opcode_info_map,int batch_size){ |
| 38 | |
| 39 | Module_info module_default; |
| 40 | module_default.module_target_info = FPGA; |
| 41 | module_default.module_type = HW_CONV; |
| 42 | module_default.module_name = "Convolution"; /// TODO abid needs to update the layer information based on the enum instead of layer name |
| 43 | module_default.num_total_ports=11; // TODO need to check with buffer management & init module |
| 44 | obj_module_opcode.mega_module = module_default; |
| 45 | |
| 46 | /*** conv mega module ports & these port order should be same as deploy file*********/ |
| 47 | |
| 48 | Port_info port_defualt; |
| 49 | port_defualt.port_width=XI_128BIT_WIDTH; |
| 50 | port_defualt.data_type = XI_INT8; |
| 51 | port_defualt.size_datatype = XI_INT8_S; |
| 52 | port_defualt.memory_align_required=32; // TODO need to check with buffer management & init module |
| 53 | port_defualt.memory_map_info = __SDS_NON_CACHEABLE; |
| 54 | port_defualt.port_enum=XI_INPUT; |
| 55 | port_defualt.qant_scheme_type = g_quant_value; |
| 56 | |
| 57 | packinfo input_pack; |
| 58 | |
| 59 | input_pack.dim = XI_CHANNEL; |
| 60 | input_pack.mem_contiguous = true; |
| 61 | input_pack.mod_div_factor = (port_defualt.port_width/port_defualt.size_datatype)/batch_size; |
| 62 | input_pack.sep=XI_DIVISION; |
| 63 | |
| 64 | port_defualt.pack_info_vec.push_back(input_pack); |
| 65 | |
| 66 | |
| 67 | |
| 68 | input_pack.dim = XI_HEIGHT; |
| 69 | input_pack.mem_contiguous = true; |
| 70 | input_pack.mod_div_factor = 0; |
| 71 | input_pack.sep=XI_NONE; |
| 72 | |
| 73 | port_defualt.pack_info_vec.push_back(input_pack); |
| 74 | |
| 75 | input_pack.dim = XI_WIDTH; |
| 76 | input_pack.mem_contiguous = true; |
| 77 | input_pack.mod_div_factor = 0; |
| 78 | input_pack.sep=XI_NONE; |
| 79 | |
| 80 | port_defualt.pack_info_vec.push_back(input_pack); |
| 81 | |
| 82 | input_pack.dim = XI_INTERLEAVED; |
| 83 | input_pack.mem_contiguous = true; |
| 84 | input_pack.mod_div_factor = (port_defualt.port_width/port_defualt.size_datatype)/batch_size; |
| 85 | input_pack.sep=XI_MODULO; |
| 86 | port_defualt.pack_info_vec.push_back(input_pack); |
| 87 | |
| 88 | input_pack.dim = XI_BATCH; |
| 89 | input_pack.mem_contiguous = true; |
| 90 | input_pack.mod_div_factor = 0; |
| 91 | input_pack.sep=XI_NONE; |
| 92 | |
| 93 | port_defualt.pack_info_vec.push_back(input_pack); |
| 94 | |