and op1, op2
| 887 | |
| 888 | // and op1, op2 |
| 889 | int x86AND(unsigned char *stream, x86Reg op1, x86Reg op2) |
| 890 | { |
| 891 | stream[0] = 0x21; |
| 892 | stream[1] = encodeRegister(op1, regCode[op2]); |
| 893 | return 2; |
| 894 | } |
| 895 | // and dword [index*mult+base+shift], op2 |
| 896 | int x86AND(unsigned char *stream, x86Size size, x86Reg index, int multiplier, x86Reg base, int shift, x86Reg op2) |
| 897 | { |
no test coverage detected