| 37 | } |
| 38 | |
| 39 | TEST(ExpressionTest, LoadExpression) { |
| 40 | std::vector<uint8_t> Vec; |
| 41 | |
| 42 | Conf.setWASMStandard(WasmEdge::Standard::WASM_1); |
| 43 | WasmEdge::Loader::Loader LdrWASM1(Conf); |
| 44 | |
| 45 | // 1. Test load limit. |
| 46 | // |
| 47 | // 1. Load invalid empty expression. |
| 48 | // 2. Load expression with only end operation. |
| 49 | // 3. Load expression with invalid operations. |
| 50 | // 4. Load expression with instructions. |
| 51 | // 5. Load expression with instructions not in proposals. |
| 52 | |
| 53 | Vec = { |
| 54 | 0x0AU, // Code section |
| 55 | 0x03U, // Content size = 3 |
| 56 | 0x01U, // Vector length = 1 |
| 57 | 0x01U, // Code segment size = 1 |
| 58 | 0x00U // Local vec(0) |
| 59 | // Expression: empty |
| 60 | }; |
| 61 | EXPECT_FALSE(Ldr.parseModule(prefixedVec(Vec))); |
| 62 | |
| 63 | Vec = { |
| 64 | 0x0AU, // Code section |
| 65 | 0x04U, // Content size = 4 |
| 66 | 0x01U, // Vector length = 1 |
| 67 | 0x02U, // Code segment size = 2 |
| 68 | 0x00U, // Local vec(0) |
| 69 | 0x0BU // Expression: OpCode End. |
| 70 | }; |
| 71 | EXPECT_TRUE(Ldr.parseModule(prefixedVec(Vec))); |
| 72 | |
| 73 | Vec = { |
| 74 | 0x0AU, // Code section |
| 75 | 0x0AU, // Content size = 10 |
| 76 | 0x01U, // Vector length = 1 |
| 77 | 0x08U, // Code segment size = 8 |
| 78 | 0x00U, // Local vec(0) |
| 79 | 0x45U, 0x46U, 0x47U, // Valid OpCodes. |
| 80 | 0xEDU, 0xEEU, 0xEFU, // Invalid OpCodes. |
| 81 | 0x0BU // OpCode End. |
| 82 | }; |
| 83 | EXPECT_FALSE(Ldr.parseModule(prefixedVec(Vec))); |
| 84 | |
| 85 | Vec = { |
| 86 | 0x0AU, // Code section |
| 87 | 0x07U, // Content size = 7 |
| 88 | 0x01U, // Vector length = 1 |
| 89 | 0x05U, // Code segment size = 5 |
| 90 | 0x00U, // Local vec(0) |
| 91 | 0x45U, 0x46U, 0x47U, // Valid OpCodes. |
| 92 | 0x0BU // OpCode End. |
| 93 | }; |
| 94 | EXPECT_TRUE(Ldr.parseModule(prefixedVec(Vec))); |
| 95 | |
| 96 | Vec = { |
nothing calls this directly
no test coverage detected