(in theory) Exactly how XED wants the world to see x86
| 751 | |
| 752 | // (in theory) Exactly how XED wants the world to see x86 |
| 753 | void X86CommonArchitecture::GetOperandTextIntel(const xed_decoded_inst_t* const xedd, const uint64_t addr, const size_t len, const xed_operand_values_t* const ov, const xed_inst_t* const xi, vector<InstructionTextToken>& result) const |
| 754 | { |
| 755 | xed_reg_enum_t extra_index_operand = XED_REG_INVALID; |
| 756 | |
| 757 | // Get operands |
| 758 | for (unsigned int opIndex = 0; opIndex < xed_inst_noperands(xi); ++opIndex) |
| 759 | { |
| 760 | const xed_operand_t* op = xed_inst_operand(xi, opIndex); |
| 761 | const xed_operand_enum_t op_name = xed_operand_name(op); |
| 762 | |
| 763 | // XED's suppressed operands shouln't be represented in Intel syntax |
| 764 | if (xed_operand_operand_visibility(op) == XED_OPVIS_SUPPRESSED) |
| 765 | { |
| 766 | if ((xed_decoded_inst_get_category(xedd) == XED_CATEGORY_STRINGOP) && |
| 767 | (op_name == XED_OPERAND_MEM0 || op_name == XED_OPERAND_MEM1)) |
| 768 | { |
| 769 | if (op_name == XED_OPERAND_MEM1) |
| 770 | result.emplace_back(OperandSeparatorToken, m_disassembly_options.separator); |
| 771 | } |
| 772 | else |
| 773 | continue; |
| 774 | } |
| 775 | |
| 776 | switch(op_name) |
| 777 | { |
| 778 | case XED_OPERAND_REG0: |
| 779 | case XED_OPERAND_REG1: |
| 780 | case XED_OPERAND_REG2: |
| 781 | case XED_OPERAND_REG3: |
| 782 | case XED_OPERAND_REG4: |
| 783 | case XED_OPERAND_REG5: |
| 784 | case XED_OPERAND_REG6: |
| 785 | case XED_OPERAND_REG7: |
| 786 | case XED_OPERAND_REG8: |
| 787 | { |
| 788 | string reg = ""; |
| 789 | |
| 790 | const xed_reg_enum_t xedReg = xed_decoded_inst_get_reg(xedd, op_name); |
| 791 | if ((xedReg >= XED_REG_X87_FIRST) && (xedReg <= XED_REG_X87_LAST)) |
| 792 | { |
| 793 | reg += "ST"; |
| 794 | reg += ('0' + (xedReg-XED_REG_X87_FIRST)); |
| 795 | } |
| 796 | else |
| 797 | { |
| 798 | reg += xed_reg_enum_t2str(xedReg); |
| 799 | } |
| 800 | if (m_disassembly_options.lowerCase) |
| 801 | for (char& c : reg) |
| 802 | c = tolower(c); |
| 803 | result.emplace_back(RegisterToken, reg); |
| 804 | break; |
| 805 | } |
| 806 | case XED_OPERAND_AGEN: |
| 807 | case XED_OPERAND_MEM0: |
| 808 | { |
| 809 | GetAddressSizeToken(xed_decoded_inst_operand_length_bits(xedd, opIndex) / 8, result, m_disassembly_options.lowerCase); |
| 810 |