The syntax used by asmx86, that users are used to (also the only one that should be garenteed to roundtrip with asm)
| 1103 | |
| 1104 | // The syntax used by asmx86, that users are used to (also the only one that should be garenteed to roundtrip with asm) |
| 1105 | void X86CommonArchitecture::GetOperandTextBNIntel(const xed_decoded_inst_t* const xedd, const uint64_t addr, const size_t len, const xed_operand_values_t* const ov, const xed_inst_t* const xi, vector<InstructionTextToken>& result) const |
| 1106 | { |
| 1107 | xed_reg_enum_t extra_index_operand = XED_REG_INVALID; |
| 1108 | |
| 1109 | // Get operands |
| 1110 | for (unsigned int opIndex = 0; opIndex < xed_inst_noperands(xi); ++opIndex) |
| 1111 | { |
| 1112 | const xed_operand_t* op = xed_inst_operand(xi, opIndex); |
| 1113 | const xed_operand_enum_t op_name = xed_operand_name(op); |
| 1114 | |
| 1115 | // XED's suppressed operands shouln't be represented in Intel syntax |
| 1116 | if (xed_operand_operand_visibility(op) == XED_OPVIS_SUPPRESSED) |
| 1117 | { |
| 1118 | if ((xed_decoded_inst_get_category(xedd) == XED_CATEGORY_STRINGOP) && |
| 1119 | (op_name == XED_OPERAND_MEM0 || op_name == XED_OPERAND_MEM1)) |
| 1120 | { |
| 1121 | if (op_name == XED_OPERAND_MEM1) |
| 1122 | result.emplace_back(OperandSeparatorToken, m_disassembly_options.separator); |
| 1123 | } |
| 1124 | else |
| 1125 | continue; |
| 1126 | } |
| 1127 | |
| 1128 | switch(op_name) |
| 1129 | { |
| 1130 | case XED_OPERAND_REG0: |
| 1131 | case XED_OPERAND_REG1: |
| 1132 | case XED_OPERAND_REG2: |
| 1133 | case XED_OPERAND_REG3: |
| 1134 | case XED_OPERAND_REG4: |
| 1135 | case XED_OPERAND_REG5: |
| 1136 | case XED_OPERAND_REG6: |
| 1137 | case XED_OPERAND_REG7: |
| 1138 | case XED_OPERAND_REG8: |
| 1139 | { |
| 1140 | string reg = ""; |
| 1141 | |
| 1142 | const xed_reg_enum_t xedReg = xed_decoded_inst_get_reg(xedd, op_name); |
| 1143 | if ((xedReg >= XED_REG_X87_FIRST) && (xedReg <= XED_REG_X87_LAST)) |
| 1144 | { |
| 1145 | reg += "ST"; |
| 1146 | reg += ('0' + (xedReg - XED_REG_X87_FIRST)); |
| 1147 | } |
| 1148 | // As of July 2020, the XED now outputs these registers as mm0, etc. |
| 1149 | // However, to maintain backward-compatibility, we need to make them mmx0, etc, |
| 1150 | // as they previously are |
| 1151 | else if ((xedReg >= XED_REG_MMX0) && (xedReg <= XED_REG_MMX1)) |
| 1152 | { |
| 1153 | reg += "MMX"; |
| 1154 | reg += ('0' + (xedReg - XED_REG_MMX0)); |
| 1155 | } |
| 1156 | else |
| 1157 | { |
| 1158 | reg += xed_reg_enum_t2str(xedReg); |
| 1159 | } |
| 1160 | |
| 1161 | if (m_disassembly_options.lowerCase) |
| 1162 | for (char& c : reg) |