For most instructions, instruction_index == operand_index, but some instructions (floating point, some others) have an implicit first operand (st0), so we have to remap things a bit Instruction index represents the 'nth' argument/opcode in the instruction, whereas the operand index is index that XED holds that operand in the instruction
| 300 | // For most instructions, instruction_index == operand_index, but some instructions (floating point, some others) have an implicit first operand (st0), so we have to remap things a bit |
| 301 | // Instruction index represents the 'nth' argument/opcode in the instruction, whereas the operand index is index that XED holds that operand in the instruction |
| 302 | static size_t WriteILOperand(LowLevelILFunction& il, const xed_decoded_inst_t* const xedd, const size_t addr, |
| 303 | const size_t instruction_index, const size_t operand_index, |
| 304 | const size_t value, size_t sizeToWrite = 0) |
| 305 | { |
| 306 | // sizeToWrite allows one to specify a part of the operand to write |
| 307 | // other than the whole |
| 308 | // this solves some of the problems we have; but not all |
| 309 | // we still need the ability to read and write a slice of the operand |
| 310 | if (sizeToWrite == 0) |
| 311 | sizeToWrite = xed_decoded_inst_operand_length(xedd, operand_index); |
| 312 | |
| 313 | const xed_operand_enum_t op_name = xed_operand_name(xed_inst_operand(xed_decoded_inst_inst(xedd), operand_index)); |
| 314 | |
| 315 | switch (op_name) |
| 316 | { |
| 317 | // Register cases |
| 318 | case XED_OPERAND_REG0: |
| 319 | case XED_OPERAND_REG1: |
| 320 | case XED_OPERAND_REG2: |
| 321 | case XED_OPERAND_REG3: |
| 322 | case XED_OPERAND_REG4: |
| 323 | case XED_OPERAND_REG5: |
| 324 | case XED_OPERAND_REG6: |
| 325 | case XED_OPERAND_REG7: |
| 326 | case XED_OPERAND_REG8: |
| 327 | case XED_OPERAND_BASE0: |
| 328 | case XED_OPERAND_BASE1: |
| 329 | return il.Operand(instruction_index, il.SetRegister(sizeToWrite, xed_decoded_inst_get_reg(xedd, op_name), value)); |
| 330 | |
| 331 | // Memory Accesses |
| 332 | case XED_OPERAND_AGEN: |
| 333 | case XED_OPERAND_MEM0: |
| 334 | case XED_OPERAND_MEM1: |
| 335 | return il.Operand(instruction_index, il.Store(sizeToWrite, GetILOperandMemoryAddress(il, xedd, addr, instruction_index, operand_index), value)); |
| 336 | |
| 337 | default: |
| 338 | return il.Undefined(); |
| 339 | } |
| 340 | } |
| 341 | |
| 342 | |
| 343 | static void ConditionalJump(Architecture* arch, LowLevelILFunction& il, size_t cond, size_t addrSize, uint64_t t, uint64_t f) |
no test coverage detected