| 427 | |
| 428 | |
| 429 | static void LoadPair( |
| 430 | Architecture* arch, |
| 431 | LowLevelILFunction& il, |
| 432 | InstructionOperand& dst1, |
| 433 | InstructionOperand& dst2, |
| 434 | InstructionOperand& src, |
| 435 | size_t addr) |
| 436 | { |
| 437 | ExprId address, value; |
| 438 | size_t dstSize = get_register_size(dst1.reg); |
| 439 | |
| 440 | if (src.cls == MEM_PRE_IDX || src.cls == MEM_POST_IDX) |
| 441 | address = ILREG(src); |
| 442 | else |
| 443 | address = ReadAddress(il, src, addr); |
| 444 | value = il.Load(dstSize * 2, address); |
| 445 | |
| 446 | if (src.cls == MEM_PRE_IDX) |
| 447 | il.AddInstruction(SetRegisterOrBranch(il, src.reg, ReadAddress(il, src, addr))); |
| 448 | |
| 449 | ExprId setReg; |
| 450 | if (arch->GetEndianness() == LittleEndian) |
| 451 | setReg = il.SetRegisterSplit(dstSize, dst2.reg, dst1.reg, value); |
| 452 | else |
| 453 | setReg = il.SetRegisterSplit(dstSize, dst1.reg, dst2.reg, value); |
| 454 | il.AddInstruction(setReg); |
| 455 | |
| 456 | if (src.cls == MEM_POST_IDX) |
| 457 | il.AddInstruction(SetRegisterOrBranch(il, src.reg, ReadAddress(il, src, addr))); |
| 458 | } |
| 459 | |
| 460 | |
| 461 | static void LoadPairExclusive( |
no test coverage detected