| 665 | } |
| 666 | |
| 667 | void LoadOrStoreWithAdjustment(InstructionOperand& src, |
| 668 | InstructionOperand& dst, |
| 669 | LowLevelILFunction& il, |
| 670 | bool load, |
| 671 | bool increment, |
| 672 | bool before) |
| 673 | { |
| 674 | if (before) |
| 675 | { |
| 676 | if (increment) |
| 677 | { |
| 678 | il.AddInstruction(il.SetRegister(get_register_size(src.reg), src.reg, |
| 679 | il.Add(get_register_size(src.reg), ILREG(src), il.Const(1, get_register_size(src.reg))))); |
| 680 | } |
| 681 | else |
| 682 | { |
| 683 | il.AddInstruction(il.SetRegister(get_register_size(src.reg), src.reg, |
| 684 | il.Sub(get_register_size(src.reg), ILREG(src), il.Const(1, get_register_size(src.reg))))); |
| 685 | } |
| 686 | } |
| 687 | |
| 688 | if (load) |
| 689 | { |
| 690 | il.AddInstruction(il.SetRegister(get_register_size(dst.reg), dst.reg, |
| 691 | il.Load(get_register_size(dst.reg), ILREG(src)))); |
| 692 | } |
| 693 | else |
| 694 | { |
| 695 | il.AddInstruction(il.Store(get_register_size(dst.reg), ILREG(dst), ILREG(src))); |
| 696 | } |
| 697 | |
| 698 | if (!before) |
| 699 | { |
| 700 | if (increment) |
| 701 | { |
| 702 | il.AddInstruction(il.SetRegister(get_register_size(src.reg), src.reg, |
| 703 | il.Add(get_register_size(src.reg), ILREG(src), il.Const(1, get_register_size(src.reg))))); |
| 704 | } |
| 705 | else |
| 706 | { |
| 707 | il.AddInstruction(il.SetRegister(get_register_size(src.reg), src.reg, |
| 708 | il.Sub(get_register_size(src.reg), ILREG(src), il.Const(1, get_register_size(src.reg))))); |
| 709 | } |
| 710 | } |
| 711 | } |
| 712 | |
| 713 | |
| 714 | bool GetLowLevelILForArmInstruction(Architecture* arch, uint64_t addr, LowLevelILFunction& il, Instruction& instr, size_t addrSize) |
nothing calls this directly
no test coverage detected