v28.d[1] -> REG_V0_D1 */
| 469 | |
| 470 | /* v28.d[1] -> REG_V0_D1 */ |
| 471 | static Register vector_reg_minimize(InstructionOperand& oper) |
| 472 | { |
| 473 | if (!IS_ASIMD_O(oper)) |
| 474 | return REG_NONE; |
| 475 | |
| 476 | if (oper.arrSpec == ARRSPEC_NONE) |
| 477 | { |
| 478 | if (oper.laneUsed) |
| 479 | return REG_NONE; // cannot have lane without an arrangement spec |
| 480 | return oper.reg[0]; |
| 481 | } |
| 482 | |
| 483 | int vidx = oper.reg[0] - REG_V0; |
| 484 | if (vidx < 0 || vidx > 31) |
| 485 | return REG_NONE; |
| 486 | |
| 487 | if (oper.laneUsed) |
| 488 | { |
| 489 | switch (oper.arrSpec) |
| 490 | { |
| 491 | case ARRSPEC_FULL: |
| 492 | return oper.reg[0]; |
| 493 | case ARRSPEC_1DOUBLE: |
| 494 | case ARRSPEC_2DOUBLES: |
| 495 | if (oper.lane >= 2) |
| 496 | return REG_NONE; |
| 497 | return v_unpack_lookup[ARRSPEC_2DOUBLES][vidx][oper.lane]; |
| 498 | case ARRSPEC_1SINGLE: |
| 499 | case ARRSPEC_2SINGLES: |
| 500 | case ARRSPEC_4SINGLES: |
| 501 | if (oper.lane >= 4) |
| 502 | return REG_NONE; |
| 503 | return v_unpack_lookup[ARRSPEC_4SINGLES][vidx][oper.lane]; |
| 504 | case ARRSPEC_1HALF: |
| 505 | case ARRSPEC_2HALVES: |
| 506 | case ARRSPEC_4HALVES: |
| 507 | case ARRSPEC_8HALVES: |
| 508 | if (oper.lane >= 8) |
| 509 | return REG_NONE; |
| 510 | return v_unpack_lookup[ARRSPEC_8HALVES][vidx][oper.lane]; |
| 511 | case ARRSPEC_1BYTE: |
| 512 | case ARRSPEC_4BYTES: |
| 513 | case ARRSPEC_8BYTES: |
| 514 | case ARRSPEC_16BYTES: |
| 515 | if (oper.lane >= 16) |
| 516 | return REG_NONE; |
| 517 | return v_unpack_lookup[ARRSPEC_16BYTES][vidx][oper.lane]; |
| 518 | default: |
| 519 | break; |
| 520 | } |
| 521 | } |
| 522 | else |
| 523 | { |
| 524 | switch (oper.arrSpec) |
| 525 | { |
| 526 | case ARRSPEC_FULL: |
| 527 | case ARRSPEC_2DOUBLES: |
| 528 | case ARRSPEC_4SINGLES: |
no outgoing calls
no test coverage detected