if we have two operands that have the same arrangement spec, instead of treating them as distinct sets of registers, see if we can consolidate the set of registers into a single larger register. This allows us to easily lift things like 'mov v0.16b, v1.16b' as 'mov v0, v1' */
| 660 | larger register. This allows us to easily lift things like 'mov v0.16b, v1.16b' as |
| 661 | 'mov v0, v1' */ |
| 662 | static int consolidate_vector( |
| 663 | InstructionOperand& operand1, |
| 664 | InstructionOperand& operand2, |
| 665 | Register *result) |
| 666 | { |
| 667 | /* make sure both our operand classes are single regs */ |
| 668 | if (operand1.operandClass != REG || operand2.operandClass != REG) |
| 669 | return 0; |
| 670 | |
| 671 | /* make sure our arrSpec's match. We need this to deal with cases where the arrSpec might |
| 672 | have different sizes, e.g. 'uxtl v2.2d, v8.2s'.*/ |
| 673 | if (operand1.arrSpec != operand2.arrSpec) |
| 674 | return 0; |
| 675 | |
| 676 | result[0] = v_consolidate_lookup[operand1.reg[0]-REG_V0][operand1.arrSpec]; |
| 677 | result[1] = v_consolidate_lookup[operand2.reg[0]-REG_V0][operand2.arrSpec]; |
| 678 | |
| 679 | return 1; |
| 680 | } |
| 681 | |
| 682 | static void LoadStoreOperandPairSize(LowLevelILFunction& il, bool load, size_t load_size, InstructionOperand& operand1, |
| 683 | InstructionOperand& operand2, InstructionOperand& operand3) |
no outgoing calls
no test coverage detected