| 735 | |
| 736 | |
| 737 | static void LoadStoreVector( |
| 738 | LowLevelILFunction& il, bool is_load, InstructionOperand& oper0, InstructionOperand& oper1, bool replicate=false) |
| 739 | { |
| 740 | /* do pre-indexing */ |
| 741 | ExprId tmp = GetILOperandPreIndex(il, oper1); |
| 742 | if (tmp) |
| 743 | il.AddInstruction(tmp); |
| 744 | |
| 745 | Register regs[16]; |
| 746 | int regs_n = unpack_vector(oper0, regs); |
| 747 | |
| 748 | /* if we pre-indexed, base sequential effective addresses off the base register */ |
| 749 | OperandClass oclass = (oper1.operandClass == MEM_PRE_IDX) ? MEM_REG : oper1.operandClass; |
| 750 | |
| 751 | int arrspec_size = 1; |
| 752 | int arrspec_count = 1; |
| 753 | |
| 754 | bool lanes = oper0.laneUsed; |
| 755 | |
| 756 | // int Q = 0; |
| 757 | // switch (oper0.arrSpec) |
| 758 | // { |
| 759 | // case ARRSPEC_8BYTES: |
| 760 | // case ARRSPEC_4HALVES: |
| 761 | // case ARRSPEC_2SINGLES: |
| 762 | // case ARRSPEC_1DOUBLE: |
| 763 | // Q = 0; |
| 764 | // break; |
| 765 | // case ARRSPEC_16BYTES: |
| 766 | // case ARRSPEC_8HALVES: |
| 767 | // case ARRSPEC_4SINGLES: |
| 768 | // case ARRSPEC_2DOUBLES: |
| 769 | // Q = 1; |
| 770 | // break; |
| 771 | // default: |
| 772 | // // should never happen unless the disassembler is broken |
| 773 | // LogWarn("Invalid arrangement specification"); |
| 774 | // return; |
| 775 | // } |
| 776 | // int enc_size = 0; |
| 777 | switch (oper0.arrSpec) |
| 778 | { |
| 779 | case ARRSPEC_1BYTE: |
| 780 | case ARRSPEC_4BYTES: |
| 781 | case ARRSPEC_8BYTES: |
| 782 | case ARRSPEC_16BYTES: |
| 783 | // enc_size = 0; |
| 784 | arrspec_size = 1; |
| 785 | break; |
| 786 | case ARRSPEC_1HALF: |
| 787 | case ARRSPEC_2HALVES: |
| 788 | case ARRSPEC_4HALVES: |
| 789 | case ARRSPEC_8HALVES: |
| 790 | // enc_size = 1; |
| 791 | arrspec_size = 2; |
| 792 | break; |
| 793 | case ARRSPEC_1SINGLE: |
| 794 | case ARRSPEC_2SINGLES: |
no test coverage detected