| 195 | } |
| 196 | |
| 197 | enum SystemOp SysOp(uint32_t op1, uint32_t CRn, uint32_t CRm, uint32_t op2) |
| 198 | { |
| 199 | // uint32_t tmp = (op1 << 11) | (CRn << 7) | (CRm << 3) | op2; |
| 200 | uint32_t tmp = (((op1 & 7) << 11) | ((CRn & 0xF) << 7) | ((CRm & 0xF) << 3) | ((op2) & 7)); |
| 201 | |
| 202 | switch (tmp) |
| 203 | { |
| 204 | case AT_OP_S1E1R: |
| 205 | case AT_OP_S1E1W: |
| 206 | case AT_OP_S1E0R: |
| 207 | case AT_OP_S1E0W: |
| 208 | case AT_OP_S1E1RP: |
| 209 | case AT_OP_S1E1WP: |
| 210 | case AT_OP_S1E1A: |
| 211 | case AT_OP_S1E2R: |
| 212 | case AT_OP_S1E2W: |
| 213 | case AT_OP_S12E1R: |
| 214 | case AT_OP_S12E1W: |
| 215 | case AT_OP_S12E0R: |
| 216 | case AT_OP_S12E0W: |
| 217 | case AT_OP_S1E2A: |
| 218 | case AT_OP_S1E3R: |
| 219 | case AT_OP_S1E3W: |
| 220 | case AT_OP_S1E3A: |
| 221 | return Sys_AT; // S1E1R |
| 222 | // case 0b00001111000000: |
| 223 | // return Sys_AT; // S1E1R |
| 224 | // case 0b10001111000000: |
| 225 | // return Sys_AT; // S1E2R |
| 226 | // case 0b11001111000000: |
| 227 | // return Sys_AT; // S1E3R |
| 228 | // case 0b00001111000001: |
| 229 | // return Sys_AT; // S1E1W |
| 230 | // case 0b00001111001001: |
| 231 | // return Sys_AT; // S1E1WP |
| 232 | // case 0b10001111000001: |
| 233 | // return Sys_AT; // S1E2W |
| 234 | // case 0b11001111000001: |
| 235 | // return Sys_AT; // S1E3W |
| 236 | // case 0b00001111000010: |
| 237 | // return Sys_AT; // S1E0R |
| 238 | // case 0b00001111000011: |
| 239 | // return Sys_AT; // S1E0W |
| 240 | // case 0b10001111000100: |
| 241 | // return Sys_AT; // S12E1R |
| 242 | // case 0b10001111000101: |
| 243 | // return Sys_AT; // S12E1W |
| 244 | // case 0b10001111000110: |
| 245 | // return Sys_AT; // S12E0R |
| 246 | // case 0b10001111000111: |
| 247 | // return Sys_AT; // S12E0W |
| 248 | case 0b01101110100001: |
| 249 | return Sys_DC; // ZVA |
| 250 | case 0b00001110110001: |
| 251 | return Sys_DC; // IVAC |
| 252 | case 0b00001110110010: |
| 253 | return Sys_DC; // ISW |
| 254 | case 0b01101111010001: |