uqxtn_advsimd.xml */
| 29394 | |
| 29395 | /* uqxtn_advsimd.xml */ |
| 29396 | int UQXTN_advsimd(context *ctx, Instruction *instr) |
| 29397 | { |
| 29398 | int rc = DECODE_STATUS_UNMATCHED; |
| 29399 | /* class iclass_sisd */ |
| 29400 | /* 01|U=1|11110|size=xx|10000|opcode=10100|10|Rn=xxxxx|Rd=xxxxx */ |
| 29401 | if((INSWORD & 0xFF3FFC00)==0x7E214800) { |
| 29402 | decode_fields32(ENC_UQXTN_ASISDMISC_N, ctx, instr); |
| 29403 | ctx->d = UINT(ctx->Rd); |
| 29404 | ctx->n = UINT(ctx->Rn); |
| 29405 | if(ctx->size==3) { |
| 29406 | UNDEFINED; |
| 29407 | } |
| 29408 | ctx->esize = (8) << (UINT(ctx->size)); |
| 29409 | ctx->datasize = ctx->esize; |
| 29410 | ctx->part = 0; |
| 29411 | ctx->elements = 1; |
| 29412 | ctx->unsigned_ = (ctx->U==1); |
| 29413 | OK(ENC_UQXTN_ASISDMISC_N); |
| 29414 | } |
| 29415 | /* class iclass_simd */ |
| 29416 | /* 0|Q=x|U=1|01110|size=xx|10000|opcode=10100|10|Rn=xxxxx|Rd=xxxxx */ |
| 29417 | if((INSWORD & 0xBF3FFC00)==0x2E214800) { |
| 29418 | decode_fields32(ENC_UQXTN_ASIMDMISC_N, ctx, instr); |
| 29419 | ctx->d = UINT(ctx->Rd); |
| 29420 | ctx->n = UINT(ctx->Rn); |
| 29421 | if(ctx->size==3) { |
| 29422 | UNDEFINED; |
| 29423 | } |
| 29424 | ctx->esize = (8) << (UINT(ctx->size)); |
| 29425 | ctx->datasize = 0x40; |
| 29426 | ctx->part = UINT(ctx->Q); |
| 29427 | ctx->elements = ((ctx->esize) ? ((ctx->datasize) / (ctx->esize)) : 0); |
| 29428 | ctx->unsigned_ = (ctx->U==1); |
| 29429 | OK(ENC_UQXTN_ASIMDMISC_N); |
| 29430 | } |
| 29431 | return rc; |
| 29432 | } |
| 29433 | |
| 29434 | /* urecpe_advsimd.xml */ |
| 29435 | int URECPE_advsimd(context *ctx, Instruction *instr) |
no test coverage detected