stlxr.xml */
| 25200 | |
| 25201 | /* stlxr.xml */ |
| 25202 | int STLXR(context *ctx, Instruction *instr) |
| 25203 | { |
| 25204 | int rc = DECODE_STATUS_UNMATCHED; |
| 25205 | /* class iclass_base_register */ |
| 25206 | /* size=1x|001000|o2=0|L=0|o1=0|Rs=xxxxx|o0=1|Rt2=(1)(1)(1)(1)(1)|Rn=xxxxx|Rt=xxxxx */ |
| 25207 | if((INSWORD & 0xBFE08000)==0x88008000) { |
| 25208 | decode_fields32(ENC_STLXR_SR32_LDSTEXCLR, ctx, instr); |
| 25209 | ctx->n = UINT(ctx->Rn); |
| 25210 | ctx->t = UINT(ctx->Rt); |
| 25211 | ctx->t2 = UINT(ctx->Rt2); |
| 25212 | ctx->s = UINT(ctx->Rs); |
| 25213 | ctx->acctype = (ctx->o0==1) ? AccType_ORDEREDATOMIC : AccType_ATOMIC; |
| 25214 | ctx->pair = FALSE; |
| 25215 | ctx->memop = (ctx->L==1) ? MemOp_LOAD : MemOp_STORE; |
| 25216 | ctx->elsize = (8) << (UINT(ctx->size)); |
| 25217 | ctx->regsize = (ctx->elsize==0x40) ? 0x40 : 0x20; |
| 25218 | ctx->datasize = (ctx->pair) ? (ctx->elsize) * (2) : ctx->elsize; |
| 25219 | ctx->tag_checked = ctx->n!=0x1f; |
| 25220 | ctx->rt_unknown = FALSE; |
| 25221 | ctx->rn_unknown = FALSE; |
| 25222 | if(ctx->memop==MemOp_LOAD && ctx->pair && ctx->t==ctx->t2) { |
| 25223 | ctx->c = ConstrainUnpredictable(Unpredictable_LDPOVERLAP); |
| 25224 | // assert |
| 25225 | // switch on constraint |
| 25226 | } |
| 25227 | if(ctx->memop==MemOp_STORE) { |
| 25228 | if(ctx->s==ctx->t || (ctx->pair && ctx->s==ctx->t2)) { |
| 25229 | ctx->c = ConstrainUnpredictable(Unpredictable_DATAOVERLAP); |
| 25230 | // assert |
| 25231 | // switch on constraint |
| 25232 | } |
| 25233 | if(ctx->s==ctx->n && ctx->n!=0x1f) { |
| 25234 | ctx->c = ConstrainUnpredictable(Unpredictable_BASEOVERLAP); |
| 25235 | // assert |
| 25236 | // switch on constraint |
| 25237 | } |
| 25238 | } |
| 25239 | if(ctx->size==2) OK(ENC_STLXR_SR32_LDSTEXCLR); |
| 25240 | if(ctx->size==3) OK(ENC_STLXR_SR64_LDSTEXCLR); |
| 25241 | } |
| 25242 | return rc; |
| 25243 | } |
| 25244 | |
| 25245 | /* stlxrb.xml */ |
| 25246 | int STLXRB(context *ctx, Instruction *instr) |
no test coverage detected