Function SRSHR_advsimd

arch/arm64/disassembler/decode2.c:23541–23584

srshr_advsimd.xml */

/* srshr_advsimd.xml */
int SRSHR_advsimd(context *ctx, Instruction *instr)
{
	int rc = DECODE_STATUS_UNMATCHED;
	/* class iclass_sisd */
	/* 01|U=0|111110|immh!=0000|immb=xxx|opcode[4:3]=00|o1=1|o0=0|opcode[0]=0|1|Rn=xxxxx|Rd=xxxxx */
	if((INSWORD & 0xFF80FC00)==0x5F002400 && (INSWORD & 0x780000)!=0x0) {
		decode_fields32(ENC_SRSHR_ASISDSHF_R, ctx, instr);
		ctx->d = UINT(ctx->Rd);
		ctx->n = UINT(ctx->Rn);
		if(SLICE(ctx->immh,3,3)!=1) {
			UNDEFINED;
		}
		ctx->esize = (8) << (3);
		ctx->datasize = ctx->esize;
		ctx->elements = 1;
		ctx->shift = ((ctx->esize) * (2))-UINT(((ctx->immh<<3)|ctx->immb));
		ctx->unsigned_ = (ctx->U==1);
		ctx->round = (ctx->o1==1);
		ctx->accumulate = (ctx->o0==1);
		OK(ENC_SRSHR_ASISDSHF_R);
	}
	/* class iclass_simd */
	/* 0|Q=x|U=0|011110|immh!=0000|immb=xxx|opcode[4:3]=00|o1=1|o0=0|opcode[0]=0|1|Rn=xxxxx|Rd=xxxxx */
	if((INSWORD & 0xBF80FC00)==0xF002400 && (INSWORD & 0x780000)!=0x0) {
		decode_fields32(ENC_SRSHR_ASIMDSHF_R, ctx, instr);
		ctx->d = UINT(ctx->Rd);
		ctx->n = UINT(ctx->Rn);
		if(ctx->immh==0) {
			SEE /* asimdimm */;
		}
		if(((SLICE(ctx->immh,3,3)<<1)|ctx->Q)==2) {
			UNDEFINED;
		}
		ctx->esize = (8) << (HighestSetBit(ctx->immh));
		ctx->datasize = (ctx->Q==1) ? 0x80 : 0x40;
		ctx->elements = ((ctx->esize) ? ((ctx->datasize) / (ctx->esize)) : 0);
		ctx->shift = ((ctx->esize) * (2))-UINT(((ctx->immh<<3)|ctx->immb));
		ctx->unsigned_ = (ctx->U==1);
		ctx->round = (ctx->o1==1);
		ctx->accumulate = (ctx->o0==1);
		OK(ENC_SRSHR_ASIMDSHF_R);
	}
	return rc;
}

/* srsra_advsimd.xml */
int SRSRA_advsimd(context *ctx, Instruction *instr)