sqrdmulh_advsimd_vec.xml */
| 22864 | |
| 22865 | /* sqrdmulh_advsimd_vec.xml */ |
| 22866 | int SQRDMULH_advsimd_vec(context *ctx, Instruction *instr) |
| 22867 | { |
| 22868 | int rc = DECODE_STATUS_UNMATCHED; |
| 22869 | /* class iclass_sisd */ |
| 22870 | /* 01|U=1|11110|size=xx|1|Rm=xxxxx|opcode=10110|1|Rn=xxxxx|Rd=xxxxx */ |
| 22871 | if((INSWORD & 0xFF20FC00)==0x7E20B400) { |
| 22872 | decode_fields32(ENC_SQRDMULH_ASISDSAME_ONLY, ctx, instr); |
| 22873 | ctx->d = UINT(ctx->Rd); |
| 22874 | ctx->n = UINT(ctx->Rn); |
| 22875 | ctx->m = UINT(ctx->Rm); |
| 22876 | if(ctx->size==3 || ctx->size==0) { |
| 22877 | UNDEFINED; |
| 22878 | } |
| 22879 | ctx->esize = (8) << (UINT(ctx->size)); |
| 22880 | ctx->datasize = ctx->esize; |
| 22881 | ctx->elements = 1; |
| 22882 | ctx->rounding = (ctx->U==1); |
| 22883 | OK(ENC_SQRDMULH_ASISDSAME_ONLY); |
| 22884 | } |
| 22885 | /* class iclass_simd */ |
| 22886 | /* 0|Q=x|U=1|01110|size=xx|1|Rm=xxxxx|opcode=10110|1|Rn=xxxxx|Rd=xxxxx */ |
| 22887 | if((INSWORD & 0xBF20FC00)==0x2E20B400) { |
| 22888 | decode_fields32(ENC_SQRDMULH_ASIMDSAME_ONLY, ctx, instr); |
| 22889 | ctx->d = UINT(ctx->Rd); |
| 22890 | ctx->n = UINT(ctx->Rn); |
| 22891 | ctx->m = UINT(ctx->Rm); |
| 22892 | if(ctx->size==3 || ctx->size==0) { |
| 22893 | UNDEFINED; |
| 22894 | } |
| 22895 | ctx->esize = (8) << (UINT(ctx->size)); |
| 22896 | ctx->datasize = (ctx->Q==1) ? 0x80 : 0x40; |
| 22897 | ctx->elements = ((ctx->esize) ? ((ctx->datasize) / (ctx->esize)) : 0); |
| 22898 | ctx->rounding = (ctx->U==1); |
| 22899 | OK(ENC_SQRDMULH_ASIMDSAME_ONLY); |
| 22900 | } |
| 22901 | return rc; |
| 22902 | } |
| 22903 | |
| 22904 | /* sqrshl_advsimd.xml */ |
| 22905 | int SQRSHL_advsimd(context *ctx, Instruction *instr) |
no test coverage detected