sqrdmlsh_advsimd_vec.xml */
| 22760 | |
| 22761 | /* sqrdmlsh_advsimd_vec.xml */ |
| 22762 | int SQRDMLSH_advsimd_vec(context *ctx, Instruction *instr) |
| 22763 | { |
| 22764 | int rc = DECODE_STATUS_UNMATCHED; |
| 22765 | /* class iclass_sisd */ |
| 22766 | /* 01|U=1|11110|size=xx|0|Rm=xxxxx|1|opcode[3:1]=000|S=1|1|Rn=xxxxx|Rd=xxxxx */ |
| 22767 | if((INSWORD & 0xFF20FC00)==0x7E008C00) { |
| 22768 | decode_fields32(ENC_SQRDMLSH_ASISDSAME2_ONLY, ctx, instr); |
| 22769 | if(!HaveQRDMLAHExt()) { |
| 22770 | UNDEFINED; |
| 22771 | } |
| 22772 | ctx->d = UINT(ctx->Rd); |
| 22773 | ctx->n = UINT(ctx->Rn); |
| 22774 | ctx->m = UINT(ctx->Rm); |
| 22775 | if(ctx->size==3 || ctx->size==0) { |
| 22776 | UNDEFINED; |
| 22777 | } |
| 22778 | ctx->esize = (8) << (UINT(ctx->size)); |
| 22779 | ctx->datasize = ctx->esize; |
| 22780 | ctx->elements = 1; |
| 22781 | ctx->rounding = TRUE; |
| 22782 | ctx->sub_op = (ctx->S==1); |
| 22783 | OK(ENC_SQRDMLSH_ASISDSAME2_ONLY); |
| 22784 | } |
| 22785 | /* class iclass_simd */ |
| 22786 | /* 0|Q=x|U=1|01110|size=xx|0|Rm=xxxxx|1|opcode[3:1]=000|S=1|1|Rn=xxxxx|Rd=xxxxx */ |
| 22787 | if((INSWORD & 0xBF20FC00)==0x2E008C00) { |
| 22788 | decode_fields32(ENC_SQRDMLSH_ASIMDSAME2_ONLY, ctx, instr); |
| 22789 | if(!HaveQRDMLAHExt()) { |
| 22790 | UNDEFINED; |
| 22791 | } |
| 22792 | ctx->d = UINT(ctx->Rd); |
| 22793 | ctx->n = UINT(ctx->Rn); |
| 22794 | ctx->m = UINT(ctx->Rm); |
| 22795 | if(ctx->size==3 || ctx->size==0) { |
| 22796 | UNDEFINED; |
| 22797 | } |
| 22798 | ctx->esize = (8) << (UINT(ctx->size)); |
| 22799 | ctx->datasize = (ctx->Q==1) ? 0x80 : 0x40; |
| 22800 | ctx->elements = ((ctx->esize) ? ((ctx->datasize) / (ctx->esize)) : 0); |
| 22801 | ctx->rounding = TRUE; |
| 22802 | ctx->sub_op = (ctx->S==1); |
| 22803 | OK(ENC_SQRDMLSH_ASIMDSAME2_ONLY); |
| 22804 | } |
| 22805 | return rc; |
| 22806 | } |
| 22807 | |
| 22808 | /* sqrdmulh_advsimd_elt.xml */ |
| 22809 | int SQRDMULH_advsimd_elt(context *ctx, Instruction *instr) |
no test coverage detected