sqrdmlah_advsimd_vec.xml */
| 22648 | |
| 22649 | /* sqrdmlah_advsimd_vec.xml */ |
| 22650 | int SQRDMLAH_advsimd_vec(context *ctx, Instruction *instr) |
| 22651 | { |
| 22652 | int rc = DECODE_STATUS_UNMATCHED; |
| 22653 | /* class iclass_sisd */ |
| 22654 | /* 01|U=1|11110|size=xx|0|Rm=xxxxx|1|opcode[3:1]=000|S=0|1|Rn=xxxxx|Rd=xxxxx */ |
| 22655 | if((INSWORD & 0xFF20FC00)==0x7E008400) { |
| 22656 | decode_fields32(ENC_SQRDMLAH_ASISDSAME2_ONLY, ctx, instr); |
| 22657 | if(!HaveQRDMLAHExt()) { |
| 22658 | UNDEFINED; |
| 22659 | } |
| 22660 | ctx->d = UINT(ctx->Rd); |
| 22661 | ctx->n = UINT(ctx->Rn); |
| 22662 | ctx->m = UINT(ctx->Rm); |
| 22663 | if(ctx->size==3 || ctx->size==0) { |
| 22664 | UNDEFINED; |
| 22665 | } |
| 22666 | ctx->esize = (8) << (UINT(ctx->size)); |
| 22667 | ctx->datasize = ctx->esize; |
| 22668 | ctx->elements = 1; |
| 22669 | ctx->rounding = TRUE; |
| 22670 | ctx->sub_op = (ctx->S==1); |
| 22671 | OK(ENC_SQRDMLAH_ASISDSAME2_ONLY); |
| 22672 | } |
| 22673 | /* class iclass_simd */ |
| 22674 | /* 0|Q=x|U=1|01110|size=xx|0|Rm=xxxxx|1|opcode[3:1]=000|S=0|1|Rn=xxxxx|Rd=xxxxx */ |
| 22675 | if((INSWORD & 0xBF20FC00)==0x2E008400) { |
| 22676 | decode_fields32(ENC_SQRDMLAH_ASIMDSAME2_ONLY, ctx, instr); |
| 22677 | if(!HaveQRDMLAHExt()) { |
| 22678 | UNDEFINED; |
| 22679 | } |
| 22680 | ctx->d = UINT(ctx->Rd); |
| 22681 | ctx->n = UINT(ctx->Rn); |
| 22682 | ctx->m = UINT(ctx->Rm); |
| 22683 | if(ctx->size==3 || ctx->size==0) { |
| 22684 | UNDEFINED; |
| 22685 | } |
| 22686 | ctx->esize = (8) << (UINT(ctx->size)); |
| 22687 | ctx->datasize = (ctx->Q==1) ? 0x80 : 0x40; |
| 22688 | ctx->elements = ((ctx->esize) ? ((ctx->datasize) / (ctx->esize)) : 0); |
| 22689 | ctx->rounding = TRUE; |
| 22690 | ctx->sub_op = (ctx->S==1); |
| 22691 | OK(ENC_SQRDMLAH_ASIMDSAME2_ONLY); |
| 22692 | } |
| 22693 | return rc; |
| 22694 | } |
| 22695 | |
| 22696 | /* sqrdmlsh_advsimd_elt.xml */ |
| 22697 | int SQRDMLSH_advsimd_elt(context *ctx, Instruction *instr) |
no test coverage detected