sqdmull_advsimd_vec.xml */
| 22510 | |
| 22511 | /* sqdmull_advsimd_vec.xml */ |
| 22512 | int SQDMULL_advsimd_vec(context *ctx, Instruction *instr) |
| 22513 | { |
| 22514 | int rc = DECODE_STATUS_UNMATCHED; |
| 22515 | /* class iclass_sisd */ |
| 22516 | /* 01|U=0|11110|size=xx|1|Rm=xxxxx|opcode=1101|00|Rn=xxxxx|Rd=xxxxx */ |
| 22517 | if((INSWORD & 0xFF20FC00)==0x5E20D000) { |
| 22518 | decode_fields32(ENC_SQDMULL_ASISDDIFF_ONLY, ctx, instr); |
| 22519 | ctx->d = UINT(ctx->Rd); |
| 22520 | ctx->n = UINT(ctx->Rn); |
| 22521 | ctx->m = UINT(ctx->Rm); |
| 22522 | if(ctx->size==0 || ctx->size==3) { |
| 22523 | UNDEFINED; |
| 22524 | } |
| 22525 | ctx->esize = (8) << (UINT(ctx->size)); |
| 22526 | ctx->datasize = ctx->esize; |
| 22527 | ctx->elements = 1; |
| 22528 | ctx->part = 0; |
| 22529 | OK(ENC_SQDMULL_ASISDDIFF_ONLY); |
| 22530 | } |
| 22531 | /* class iclass_simd */ |
| 22532 | /* 0|Q=x|U=0|01110|size=xx|1|Rm=xxxxx|opcode=1101|00|Rn=xxxxx|Rd=xxxxx */ |
| 22533 | if((INSWORD & 0xBF20FC00)==0xE20D000) { |
| 22534 | decode_fields32(ENC_SQDMULL_ASIMDDIFF_L, ctx, instr); |
| 22535 | ctx->d = UINT(ctx->Rd); |
| 22536 | ctx->n = UINT(ctx->Rn); |
| 22537 | ctx->m = UINT(ctx->Rm); |
| 22538 | if(ctx->size==0 || ctx->size==3) { |
| 22539 | UNDEFINED; |
| 22540 | } |
| 22541 | ctx->esize = (8) << (UINT(ctx->size)); |
| 22542 | ctx->datasize = 0x40; |
| 22543 | ctx->part = UINT(ctx->Q); |
| 22544 | ctx->elements = ((ctx->esize) ? ((ctx->datasize) / (ctx->esize)) : 0); |
| 22545 | OK(ENC_SQDMULL_ASIMDDIFF_L); |
| 22546 | } |
| 22547 | return rc; |
| 22548 | } |
| 22549 | |
| 22550 | /* sqneg_advsimd.xml */ |
| 22551 | int SQNEG_advsimd(context *ctx, Instruction *instr) |
no test coverage detected