sqdmulh_advsimd_vec.xml */
| 22414 | |
| 22415 | /* sqdmulh_advsimd_vec.xml */ |
| 22416 | int SQDMULH_advsimd_vec(context *ctx, Instruction *instr) |
| 22417 | { |
| 22418 | int rc = DECODE_STATUS_UNMATCHED; |
| 22419 | /* class iclass_sisd */ |
| 22420 | /* 01|U=0|11110|size=xx|1|Rm=xxxxx|opcode=10110|1|Rn=xxxxx|Rd=xxxxx */ |
| 22421 | if((INSWORD & 0xFF20FC00)==0x5E20B400) { |
| 22422 | decode_fields32(ENC_SQDMULH_ASISDSAME_ONLY, ctx, instr); |
| 22423 | ctx->d = UINT(ctx->Rd); |
| 22424 | ctx->n = UINT(ctx->Rn); |
| 22425 | ctx->m = UINT(ctx->Rm); |
| 22426 | if(ctx->size==3 || ctx->size==0) { |
| 22427 | UNDEFINED; |
| 22428 | } |
| 22429 | ctx->esize = (8) << (UINT(ctx->size)); |
| 22430 | ctx->datasize = ctx->esize; |
| 22431 | ctx->elements = 1; |
| 22432 | ctx->rounding = (ctx->U==1); |
| 22433 | OK(ENC_SQDMULH_ASISDSAME_ONLY); |
| 22434 | } |
| 22435 | /* class iclass_simd */ |
| 22436 | /* 0|Q=x|U=0|01110|size=xx|1|Rm=xxxxx|opcode=10110|1|Rn=xxxxx|Rd=xxxxx */ |
| 22437 | if((INSWORD & 0xBF20FC00)==0xE20B400) { |
| 22438 | decode_fields32(ENC_SQDMULH_ASIMDSAME_ONLY, ctx, instr); |
| 22439 | ctx->d = UINT(ctx->Rd); |
| 22440 | ctx->n = UINT(ctx->Rn); |
| 22441 | ctx->m = UINT(ctx->Rm); |
| 22442 | if(ctx->size==3 || ctx->size==0) { |
| 22443 | UNDEFINED; |
| 22444 | } |
| 22445 | ctx->esize = (8) << (UINT(ctx->size)); |
| 22446 | ctx->datasize = (ctx->Q==1) ? 0x80 : 0x40; |
| 22447 | ctx->elements = ((ctx->esize) ? ((ctx->datasize) / (ctx->esize)) : 0); |
| 22448 | ctx->rounding = (ctx->U==1); |
| 22449 | OK(ENC_SQDMULH_ASIMDSAME_ONLY); |
| 22450 | } |
| 22451 | return rc; |
| 22452 | } |
| 22453 | |
| 22454 | /* sqdmull_advsimd_elt.xml */ |
| 22455 | int SQDMULL_advsimd_elt(context *ctx, Instruction *instr) |
no test coverage detected