rev.xml */
| 19702 | |
| 19703 | /* rev.xml */ |
| 19704 | int REV(context *ctx, Instruction *instr) |
| 19705 | { |
| 19706 | int rc = DECODE_STATUS_UNMATCHED; |
| 19707 | /* class iclass_general */ |
| 19708 | /* sf=x|1|S=0|11010110|opcode2=00000|opcode[5:2]=0000|opc=1x|Rn=xxxxx|Rd=xxxxx */ |
| 19709 | if((INSWORD & 0x7FFFF800)==0x5AC00800) { |
| 19710 | decode_fields32(ENC_REV_32_DP_1SRC, ctx, instr); |
| 19711 | ctx->d = UINT(ctx->Rd); |
| 19712 | ctx->n = UINT(ctx->Rn); |
| 19713 | ctx->datasize = (ctx->sf==1) ? 0x40 : 0x20; |
| 19714 | if(!ctx->opc) { |
| 19715 | ENDOFINSTRUCTION; |
| 19716 | } |
| 19717 | else if(ctx->opc==1) { |
| 19718 | ctx->container_size = 0x10; |
| 19719 | } |
| 19720 | else if(ctx->opc==2) { |
| 19721 | ctx->container_size = 0x20; |
| 19722 | } |
| 19723 | else if(ctx->opc==3) { |
| 19724 | if(ctx->sf==0) { |
| 19725 | UNDEFINED; |
| 19726 | } |
| 19727 | ctx->container_size = 0x40; |
| 19728 | } |
| 19729 | if(ctx->sf==0 && ctx->opc==2) OK(ENC_REV_32_DP_1SRC); |
| 19730 | if(ctx->sf==1 && ctx->opc==3) OK(ENC_REV_64_DP_1SRC); |
| 19731 | } |
| 19732 | return rc; |
| 19733 | } |
| 19734 | |
| 19735 | /* rev16_advsimd.xml */ |
| 19736 | int REV16_advsimd(context *ctx, Instruction *instr) |
no test coverage detected