ldxr.xml */
| 17091 | |
| 17092 | /* ldxr.xml */ |
| 17093 | int LDXR(context *ctx, Instruction *instr) |
| 17094 | { |
| 17095 | int rc = DECODE_STATUS_UNMATCHED; |
| 17096 | /* class iclass_base_register */ |
| 17097 | /* size=1x|001000|o2=0|L=1|o1=0|Rs=(1)(1)(1)(1)(1)|o0=0|Rt2=(1)(1)(1)(1)(1)|Rn=xxxxx|Rt=xxxxx */ |
| 17098 | if((INSWORD & 0xBFE08000)==0x88400000) { |
| 17099 | decode_fields32(ENC_LDXR_LR32_LDSTEXCLR, ctx, instr); |
| 17100 | ctx->n = UINT(ctx->Rn); |
| 17101 | ctx->t = UINT(ctx->Rt); |
| 17102 | ctx->t2 = UINT(ctx->Rt2); |
| 17103 | ctx->s = UINT(ctx->Rs); |
| 17104 | ctx->acctype = (ctx->o0==1) ? AccType_ORDEREDATOMIC : AccType_ATOMIC; |
| 17105 | ctx->pair = FALSE; |
| 17106 | ctx->memop = (ctx->L==1) ? MemOp_LOAD : MemOp_STORE; |
| 17107 | ctx->elsize = (8) << (UINT(ctx->size)); |
| 17108 | ctx->regsize = (ctx->elsize==0x40) ? 0x40 : 0x20; |
| 17109 | ctx->datasize = (ctx->pair) ? (ctx->elsize) * (2) : ctx->elsize; |
| 17110 | ctx->tag_checked = ctx->n!=0x1f; |
| 17111 | ctx->rt_unknown = FALSE; |
| 17112 | ctx->rn_unknown = FALSE; |
| 17113 | if(ctx->memop==MemOp_LOAD && ctx->pair && ctx->t==ctx->t2) { |
| 17114 | ctx->c = ConstrainUnpredictable(Unpredictable_LDPOVERLAP); |
| 17115 | // assert |
| 17116 | // switch on constraint |
| 17117 | } |
| 17118 | if(ctx->memop==MemOp_STORE) { |
| 17119 | if(ctx->s==ctx->t || (ctx->pair && ctx->s==ctx->t2)) { |
| 17120 | ctx->c = ConstrainUnpredictable(Unpredictable_DATAOVERLAP); |
| 17121 | // assert |
| 17122 | // switch on constraint |
| 17123 | } |
| 17124 | if(ctx->s==ctx->n && ctx->n!=0x1f) { |
| 17125 | ctx->c = ConstrainUnpredictable(Unpredictable_BASEOVERLAP); |
| 17126 | // assert |
| 17127 | // switch on constraint |
| 17128 | } |
| 17129 | } |
| 17130 | if(ctx->size==2) OK(ENC_LDXR_LR32_LDSTEXCLR); |
| 17131 | if(ctx->size==3) OK(ENC_LDXR_LR64_LDSTEXCLR); |
| 17132 | } |
| 17133 | return rc; |
| 17134 | } |
| 17135 | |
| 17136 | /* ldxrb.xml */ |
| 17137 | int LDXRB(context *ctx, Instruction *instr) |
no test coverage detected