Function LDAXRH

arch/arm64/disassembler/decode2.c:13602–13642

ldaxrh.xml */

/* ldaxrh.xml */
int LDAXRH(context *ctx, Instruction *instr)
{
	int rc = DECODE_STATUS_UNMATCHED;
	/* class iclass_base_register */
	/* size=01|001000|o2=0|L=1|o1=0|Rs=(1)(1)(1)(1)(1)|o0=1|Rt2=(1)(1)(1)(1)(1)|Rn=xxxxx|Rt=xxxxx */
	if((INSWORD & 0xFFE08000)==0x48408000) {
		decode_fields32(ENC_LDAXRH_LR32_LDSTEXCLR, ctx, instr);
		ctx->n = UINT(ctx->Rn);
		ctx->t = UINT(ctx->Rt);
		ctx->t2 = UINT(ctx->Rt2);
		ctx->s = UINT(ctx->Rs);
		ctx->acctype = (ctx->o0==1) ? AccType_ORDEREDATOMIC : AccType_ATOMIC;
		ctx->pair = FALSE;
		ctx->memop = (ctx->L==1) ? MemOp_LOAD : MemOp_STORE;
		ctx->elsize = (8) << (UINT(ctx->size));
		ctx->regsize = (ctx->elsize==0x40) ? 0x40 : 0x20;
		ctx->datasize = (ctx->pair) ? (ctx->elsize) * (2) : ctx->elsize;
		ctx->tag_checked = ctx->n!=0x1f;
		ctx->rt_unknown = FALSE;
		ctx->rn_unknown = FALSE;
		if(ctx->memop==MemOp_LOAD && ctx->pair && ctx->t==ctx->t2) {
			ctx->c = ConstrainUnpredictable(Unpredictable_LDPOVERLAP);
			// assert
			// switch on constraint
		}
		if(ctx->memop==MemOp_STORE) {
			if(ctx->s==ctx->t || (ctx->pair && ctx->s==ctx->t2)) {
				ctx->c = ConstrainUnpredictable(Unpredictable_DATAOVERLAP);
				// assert
				// switch on constraint
			}
			if(ctx->s==ctx->n && ctx->n!=0x1f) {
				ctx->c = ConstrainUnpredictable(Unpredictable_BASEOVERLAP);
				// assert
				// switch on constraint
			}
		}
		OK(ENC_LDAXRH_LR32_LDSTEXCLR);
	}
	return rc;
}

/* ldclr.xml */
int LDCLR(context *ctx, Instruction *instr)