ldaxr.xml */
| 13513 | |
| 13514 | /* ldaxr.xml */ |
| 13515 | int LDAXR(context *ctx, Instruction *instr) |
| 13516 | { |
| 13517 | int rc = DECODE_STATUS_UNMATCHED; |
| 13518 | /* class iclass_base_register */ |
| 13519 | /* size=1x|001000|o2=0|L=1|o1=0|Rs=(1)(1)(1)(1)(1)|o0=1|Rt2=(1)(1)(1)(1)(1)|Rn=xxxxx|Rt=xxxxx */ |
| 13520 | if((INSWORD & 0xBFE08000)==0x88408000) { |
| 13521 | decode_fields32(ENC_LDAXR_LR32_LDSTEXCLR, ctx, instr); |
| 13522 | ctx->n = UINT(ctx->Rn); |
| 13523 | ctx->t = UINT(ctx->Rt); |
| 13524 | ctx->t2 = UINT(ctx->Rt2); |
| 13525 | ctx->s = UINT(ctx->Rs); |
| 13526 | ctx->acctype = (ctx->o0==1) ? AccType_ORDEREDATOMIC : AccType_ATOMIC; |
| 13527 | ctx->pair = FALSE; |
| 13528 | ctx->memop = (ctx->L==1) ? MemOp_LOAD : MemOp_STORE; |
| 13529 | ctx->elsize = (8) << (UINT(ctx->size)); |
| 13530 | ctx->regsize = (ctx->elsize==0x40) ? 0x40 : 0x20; |
| 13531 | ctx->datasize = (ctx->pair) ? (ctx->elsize) * (2) : ctx->elsize; |
| 13532 | ctx->tag_checked = ctx->n!=0x1f; |
| 13533 | ctx->rt_unknown = FALSE; |
| 13534 | ctx->rn_unknown = FALSE; |
| 13535 | if(ctx->memop==MemOp_LOAD && ctx->pair && ctx->t==ctx->t2) { |
| 13536 | ctx->c = ConstrainUnpredictable(Unpredictable_LDPOVERLAP); |
| 13537 | // assert |
| 13538 | // switch on constraint |
| 13539 | } |
| 13540 | if(ctx->memop==MemOp_STORE) { |
| 13541 | if(ctx->s==ctx->t || (ctx->pair && ctx->s==ctx->t2)) { |
| 13542 | ctx->c = ConstrainUnpredictable(Unpredictable_DATAOVERLAP); |
| 13543 | // assert |
| 13544 | // switch on constraint |
| 13545 | } |
| 13546 | if(ctx->s==ctx->n && ctx->n!=0x1f) { |
| 13547 | ctx->c = ConstrainUnpredictable(Unpredictable_BASEOVERLAP); |
| 13548 | // assert |
| 13549 | // switch on constraint |
| 13550 | } |
| 13551 | } |
| 13552 | if(ctx->size==2) OK(ENC_LDAXR_LR32_LDSTEXCLR); |
| 13553 | if(ctx->size==3) OK(ENC_LDAXR_LR64_LDSTEXCLR); |
| 13554 | } |
| 13555 | return rc; |
| 13556 | } |
| 13557 | |
| 13558 | /* ldaxrb.xml */ |
| 13559 | int LDAXRB(context *ctx, Instruction *instr) |
no test coverage detected