Function LD4_advsimd_mult

arch/arm64/disassembler/decode2.c:12630–12696

ld4_advsimd_mult.xml */

/* ld4_advsimd_mult.xml */
int LD4_advsimd_mult(context *ctx, Instruction *instr)
{
	int rc = DECODE_STATUS_UNMATCHED;
	/* class iclass_as_no_post_index */
	/* 0|Q=x|0011000|L=1|000000|opcode=0000|size=xx|Rn=xxxxx|Rt=xxxxx */
	if((INSWORD & 0xBFFFF000)==0xC400000) {
		decode_fields32(ENC_LD4_ASISDLSE_R4, ctx, instr);
		ctx->t = UINT(ctx->Rt);
		ctx->n = UINT(ctx->Rn);
		ctx->m = 0;
		ctx->wback = FALSE;
		ctx->tag_checked = ctx->wback || ctx->n!=0x1f;
		OK(ENC_LD4_ASISDLSE_R4);
	}
	/* class iclass_as_post_index */
	/* 0|Q=x|0011001|L=1|0|Rm=xxxxx|opcode=0000|size=xx|Rn=xxxxx|Rt=xxxxx */
	if((INSWORD & 0xBFE0F000)==0xCC00000) {
		decode_fields32(ENC_LD4_ASISDLSEP_I4_I, ctx, instr);
		ctx->t = UINT(ctx->Rt);
		ctx->n = UINT(ctx->Rn);
		ctx->m = UINT(ctx->Rm);
		ctx->wback = TRUE;
		ctx->tag_checked = ctx->wback || ctx->n!=0x1f;
		if(ctx->Rm==0x1f) OK(ENC_LD4_ASISDLSEP_I4_I);
		if(ctx->Rm!=0x1f) OK(ENC_LD4_ASISDLSEP_R4_R);
	}
	/* post-decode pcode */
	ctx->memop = (ctx->L==1) ? MemOp_LOAD : MemOp_STORE;
	ctx->datasize = (ctx->Q==1) ? 0x80 : 0x40;
	ctx->esize = (8) << (UINT(ctx->size));
	ctx->elements = ((ctx->esize) ? ((ctx->datasize) / (ctx->esize)) : 0);
	if(!ctx->opcode) {
		ctx->rpt = 1;
		ctx->selem = 4;
	}
	else if(ctx->opcode==2) {
		ctx->rpt = 4;
		ctx->selem = 1;
	}
	else if(ctx->opcode==4) {
		ctx->rpt = 1;
		ctx->selem = 3;
	}
	else if(ctx->opcode==6) {
		ctx->rpt = 3;
		ctx->selem = 1;
	}
	else if(ctx->opcode==7) {
		ctx->rpt = 1;
		ctx->selem = 1;
	}
	else if(ctx->opcode==8) {
		ctx->rpt = 1;
		ctx->selem = 2;
	}
	else if(ctx->opcode==10) {
		ctx->rpt = 2;
		ctx->selem = 1;