Function LD4R_advsimd

arch/arm64/disassembler/decode2.c:12561–12627

ld4r_advsimd.xml */

/* ld4r_advsimd.xml */
int LD4R_advsimd(context *ctx, Instruction *instr)
{
	int rc = DECODE_STATUS_UNMATCHED;
	/* class iclass_as_no_post_index */
	/* 0|Q=x|0011010|L=1|R=1|00000|opcode=111|S=0|size=xx|Rn=xxxxx|Rt=xxxxx */
	if((INSWORD & 0xBFFFF000)==0xD60E000) {
		decode_fields32(ENC_LD4R_ASISDLSO_R4, ctx, instr);
		ctx->t = UINT(ctx->Rt);
		ctx->n = UINT(ctx->Rn);
		ctx->m = 0;
		ctx->wback = FALSE;
		ctx->tag_checked = ctx->wback || ctx->n!=0x1f;
		OK(ENC_LD4R_ASISDLSO_R4);
	}
	/* class iclass_as_post_index */
	/* 0|Q=x|0011011|L=1|R=1|Rm=xxxxx|opcode=111|S=0|size=xx|Rn=xxxxx|Rt=xxxxx */
	if((INSWORD & 0xBFE0F000)==0xDE0E000) {
		decode_fields32(ENC_LD4R_ASISDLSOP_R4_I, ctx, instr);
		ctx->t = UINT(ctx->Rt);
		ctx->n = UINT(ctx->Rn);
		ctx->m = UINT(ctx->Rm);
		ctx->wback = TRUE;
		ctx->tag_checked = ctx->wback || ctx->n!=0x1f;
		if(ctx->Rm==0x1f) OK(ENC_LD4R_ASISDLSOP_R4_I);
		if(ctx->Rm!=0x1f) OK(ENC_LD4R_ASISDLSOP_RX4_R);
	}
	/* post-decode pcode */
	ctx->init_scale = UINT(SLICE(ctx->opcode,2,1));
	ctx->scale = ctx->init_scale;
	ctx->selem = UINT(((SLICE(ctx->opcode,0,0)<<1)|ctx->R))+1;
	ctx->replicate = FALSE;
	if(ctx->scale==3) {
		if(ctx->L==0 || ctx->S==1) {
			UNDEFINED;
		}
		ctx->scale = UINT(ctx->size);
		ctx->replicate = TRUE;
	}
	else if(ctx->scale==0) {
		ctx->index = UINT(((ctx->Q<<3)|(ctx->S<<2)|ctx->size));
	}
	else if(ctx->scale==1) {
		if(SLICE(ctx->size,0,0)==1) {
			UNDEFINED;
		}
		ctx->index = UINT(((ctx->Q<<2)|(ctx->S<<1)|SLICE(ctx->size,1,1)));
	}
	else if(ctx->scale==2) {
		if(SLICE(ctx->size,1,1)==1) {
			UNDEFINED;
		}
		if(SLICE(ctx->size,0,0)==0) {
			ctx->index = UINT(((ctx->Q<<1)|ctx->S));
		}
		else {
			if(ctx->S==1) {
				UNDEFINED;
			}