fsqrt_float.xml */
| 11525 | |
| 11526 | /* fsqrt_float.xml */ |
| 11527 | int FSQRT_float(context *ctx, Instruction *instr) |
| 11528 | { |
| 11529 | int rc = DECODE_STATUS_UNMATCHED; |
| 11530 | /* class iclass_float */ |
| 11531 | /* M=0|0|S=0|11110|ftype=xx|1|opcode[5:2]=0000|opc=11|10000|Rn=xxxxx|Rd=xxxxx */ |
| 11532 | if((INSWORD & 0xFF3FFC00)==0x1E21C000) { |
| 11533 | decode_fields32(ENC_FSQRT_H_FLOATDP1, ctx, instr); |
| 11534 | ctx->d = UINT(ctx->Rd); |
| 11535 | ctx->n = UINT(ctx->Rn); |
| 11536 | if(!ctx->ftype) { |
| 11537 | ctx->esize = 0x20; |
| 11538 | } |
| 11539 | else if(ctx->ftype==1) { |
| 11540 | ctx->esize = 0x40; |
| 11541 | } |
| 11542 | else if(ctx->ftype==2) { |
| 11543 | UNDEFINED; |
| 11544 | } |
| 11545 | else if(ctx->ftype==3) { |
| 11546 | if(HaveFP16Ext()) { |
| 11547 | ctx->esize = 0x10; |
| 11548 | } |
| 11549 | else { |
| 11550 | UNDEFINED; |
| 11551 | } |
| 11552 | } |
| 11553 | if(!ctx->opc) { |
| 11554 | ctx->fpop = FPUnaryOp_MOV; |
| 11555 | } |
| 11556 | else if(ctx->opc==1) { |
| 11557 | ctx->fpop = FPUnaryOp_ABS; |
| 11558 | } |
| 11559 | else if(ctx->opc==2) { |
| 11560 | ctx->fpop = FPUnaryOp_NEG; |
| 11561 | } |
| 11562 | else if(ctx->opc==3) { |
| 11563 | ctx->fpop = FPUnaryOp_SQRT; |
| 11564 | } |
| 11565 | if(ctx->ftype==3) OK(ENC_FSQRT_H_FLOATDP1); |
| 11566 | if(ctx->ftype==0) OK(ENC_FSQRT_S_FLOATDP1); |
| 11567 | if(ctx->ftype==1) OK(ENC_FSQRT_D_FLOATDP1); |
| 11568 | } |
| 11569 | return rc; |
| 11570 | } |
| 11571 | |
| 11572 | /* fsub_advsimd.xml */ |
| 11573 | int FSUB_advsimd(context *ctx, Instruction *instr) |
no test coverage detected