fmlsl_advsimd_vec.xml */
| 9116 | |
| 9117 | /* fmlsl_advsimd_vec.xml */ |
| 9118 | int FMLSL_advsimd_vec(context *ctx, Instruction *instr) |
| 9119 | { |
| 9120 | int rc = DECODE_STATUS_UNMATCHED; |
| 9121 | /* class iclass_fmlsl */ |
| 9122 | /* 0|Q=x|U=0|01110|S=1|sz=0|1|Rm=xxxxx|opcode[4]=1|opcode[3:0]=1101|1|Rn=xxxxx|Rd=xxxxx */ |
| 9123 | if((INSWORD & 0xBFE0FC00)==0xEA0EC00) { |
| 9124 | decode_fields32(ENC_FMLSL_ASIMDSAME_F, ctx, instr); |
| 9125 | if(!HaveFP16MulNoRoundingToFP32Ext()) { |
| 9126 | UNDEFINED; |
| 9127 | } |
| 9128 | ctx->d = UINT(ctx->Rd); |
| 9129 | ctx->n = UINT(ctx->Rn); |
| 9130 | ctx->m = UINT(ctx->Rm); |
| 9131 | if(ctx->sz==1) { |
| 9132 | UNDEFINED; |
| 9133 | } |
| 9134 | ctx->esize = 0x20; |
| 9135 | ctx->datasize = (ctx->Q==1) ? 0x80 : 0x40; |
| 9136 | ctx->elements = ((ctx->esize) ? ((ctx->datasize) / (ctx->esize)) : 0); |
| 9137 | ctx->sub_op = (ctx->S==1); |
| 9138 | ctx->part = 0; |
| 9139 | OK(ENC_FMLSL_ASIMDSAME_F); |
| 9140 | } |
| 9141 | /* class iclass_fmlsl2 */ |
| 9142 | /* 0|Q=x|U=1|01110|S=1|sz=0|1|Rm=xxxxx|opcode[4]=1|opcode[3:0]=1001|1|Rn=xxxxx|Rd=xxxxx */ |
| 9143 | if((INSWORD & 0xBFE0FC00)==0x2EA0CC00) { |
| 9144 | decode_fields32(ENC_FMLSL2_ASIMDSAME_F, ctx, instr); |
| 9145 | if(!HaveFP16MulNoRoundingToFP32Ext()) { |
| 9146 | UNDEFINED; |
| 9147 | } |
| 9148 | ctx->d = UINT(ctx->Rd); |
| 9149 | ctx->n = UINT(ctx->Rn); |
| 9150 | ctx->m = UINT(ctx->Rm); |
| 9151 | if(ctx->sz==1) { |
| 9152 | UNDEFINED; |
| 9153 | } |
| 9154 | ctx->esize = 0x20; |
| 9155 | ctx->datasize = (ctx->Q==1) ? 0x80 : 0x40; |
| 9156 | ctx->elements = ((ctx->esize) ? ((ctx->datasize) / (ctx->esize)) : 0); |
| 9157 | ctx->sub_op = (ctx->S==1); |
| 9158 | ctx->part = 1; |
| 9159 | OK(ENC_FMLSL2_ASIMDSAME_F); |
| 9160 | } |
| 9161 | return rc; |
| 9162 | } |
| 9163 | |
| 9164 | /* fmls_advsimd_elt.xml */ |
| 9165 | int FMLS_advsimd_elt(context *ctx, Instruction *instr) |
no test coverage detected