fmlal_advsimd_vec.xml */
| 8887 | |
| 8888 | /* fmlal_advsimd_vec.xml */ |
| 8889 | int FMLAL_advsimd_vec(context *ctx, Instruction *instr) |
| 8890 | { |
| 8891 | int rc = DECODE_STATUS_UNMATCHED; |
| 8892 | /* class iclass_fmlal */ |
| 8893 | /* 0|Q=x|U=0|01110|S=0|sz=0|1|Rm=xxxxx|opcode[4]=1|opcode[3:0]=1101|1|Rn=xxxxx|Rd=xxxxx */ |
| 8894 | if((INSWORD & 0xBFE0FC00)==0xE20EC00) { |
| 8895 | decode_fields32(ENC_FMLAL_ASIMDSAME_F, ctx, instr); |
| 8896 | if(!HaveFP16MulNoRoundingToFP32Ext()) { |
| 8897 | UNDEFINED; |
| 8898 | } |
| 8899 | ctx->d = UINT(ctx->Rd); |
| 8900 | ctx->n = UINT(ctx->Rn); |
| 8901 | ctx->m = UINT(ctx->Rm); |
| 8902 | if(ctx->sz==1) { |
| 8903 | UNDEFINED; |
| 8904 | } |
| 8905 | ctx->esize = 0x20; |
| 8906 | ctx->datasize = (ctx->Q==1) ? 0x80 : 0x40; |
| 8907 | ctx->elements = ((ctx->esize) ? ((ctx->datasize) / (ctx->esize)) : 0); |
| 8908 | ctx->sub_op = (ctx->S==1); |
| 8909 | ctx->part = 0; |
| 8910 | OK(ENC_FMLAL_ASIMDSAME_F); |
| 8911 | } |
| 8912 | /* class iclass_fmlal2 */ |
| 8913 | /* 0|Q=x|U=1|01110|S=0|sz=0|1|Rm=xxxxx|opcode[4]=1|opcode[3:0]=1001|1|Rn=xxxxx|Rd=xxxxx */ |
| 8914 | if((INSWORD & 0xBFE0FC00)==0x2E20CC00) { |
| 8915 | decode_fields32(ENC_FMLAL2_ASIMDSAME_F, ctx, instr); |
| 8916 | if(!HaveFP16MulNoRoundingToFP32Ext()) { |
| 8917 | UNDEFINED; |
| 8918 | } |
| 8919 | ctx->d = UINT(ctx->Rd); |
| 8920 | ctx->n = UINT(ctx->Rn); |
| 8921 | ctx->m = UINT(ctx->Rm); |
| 8922 | if(ctx->sz==1) { |
| 8923 | UNDEFINED; |
| 8924 | } |
| 8925 | ctx->esize = 0x20; |
| 8926 | ctx->datasize = (ctx->Q==1) ? 0x80 : 0x40; |
| 8927 | ctx->elements = ((ctx->esize) ? ((ctx->datasize) / (ctx->esize)) : 0); |
| 8928 | ctx->sub_op = (ctx->S==1); |
| 8929 | ctx->part = 1; |
| 8930 | OK(ENC_FMLAL2_ASIMDSAME_F); |
| 8931 | } |
| 8932 | return rc; |
| 8933 | } |
| 8934 | |
| 8935 | /* fmla_advsimd_elt.xml */ |
| 8936 | int FMLA_advsimd_elt(context *ctx, Instruction *instr) |
no test coverage detected