fmlal_advsimd_elt.xml */
| 8838 | |
| 8839 | /* fmlal_advsimd_elt.xml */ |
| 8840 | int FMLAL_advsimd_elt(context *ctx, Instruction *instr) |
| 8841 | { |
| 8842 | int rc = DECODE_STATUS_UNMATCHED; |
| 8843 | /* class iclass_fmlal */ |
| 8844 | /* 0|Q=x|U=0|01111|size[1]=1|sz=0|L=x|M=x|Rm=xxxx|opcode[3]=0|S=0|opcode[1:0]=00|H=x|0|Rn=xxxxx|Rd=xxxxx */ |
| 8845 | if((INSWORD & 0xBFC0F400)==0xF800000) { |
| 8846 | decode_fields32(ENC_FMLAL_ASIMDELEM_LH, ctx, instr); |
| 8847 | if(!HaveFP16MulNoRoundingToFP32Ext()) { |
| 8848 | UNDEFINED; |
| 8849 | } |
| 8850 | ctx->d = UINT(ctx->Rd); |
| 8851 | ctx->n = UINT(ctx->Rn); |
| 8852 | ctx->m = UINT(ctx->Rm); |
| 8853 | if(ctx->sz==1) { |
| 8854 | UNDEFINED; |
| 8855 | } |
| 8856 | ctx->index = UINT(((ctx->H<<2)|(ctx->L<<1)|ctx->M)); |
| 8857 | ctx->esize = 0x20; |
| 8858 | ctx->datasize = (ctx->Q==1) ? 0x80 : 0x40; |
| 8859 | ctx->elements = ((ctx->esize) ? ((ctx->datasize) / (ctx->esize)) : 0); |
| 8860 | ctx->sub_op = (ctx->S==1); |
| 8861 | ctx->part = 0; |
| 8862 | OK(ENC_FMLAL_ASIMDELEM_LH); |
| 8863 | } |
| 8864 | /* class iclass_fmlal2 */ |
| 8865 | /* 0|Q=x|U=1|01111|size[1]=1|sz=0|L=x|M=x|Rm=xxxx|opcode[3]=1|S=0|opcode[1:0]=00|H=x|0|Rn=xxxxx|Rd=xxxxx */ |
| 8866 | if((INSWORD & 0xBFC0F400)==0x2F808000) { |
| 8867 | decode_fields32(ENC_FMLAL2_ASIMDELEM_LH, ctx, instr); |
| 8868 | if(!HaveFP16MulNoRoundingToFP32Ext()) { |
| 8869 | UNDEFINED; |
| 8870 | } |
| 8871 | ctx->d = UINT(ctx->Rd); |
| 8872 | ctx->n = UINT(ctx->Rn); |
| 8873 | ctx->m = UINT(ctx->Rm); |
| 8874 | if(ctx->sz==1) { |
| 8875 | UNDEFINED; |
| 8876 | } |
| 8877 | ctx->index = UINT(((ctx->H<<2)|(ctx->L<<1)|ctx->M)); |
| 8878 | ctx->esize = 0x20; |
| 8879 | ctx->datasize = (ctx->Q==1) ? 0x80 : 0x40; |
| 8880 | ctx->elements = ((ctx->esize) ? ((ctx->datasize) / (ctx->esize)) : 0); |
| 8881 | ctx->sub_op = (ctx->S==1); |
| 8882 | ctx->part = 1; |
| 8883 | OK(ENC_FMLAL2_ASIMDELEM_LH); |
| 8884 | } |
| 8885 | return rc; |
| 8886 | } |
| 8887 | |
| 8888 | /* fmlal_advsimd_vec.xml */ |
| 8889 | int FMLAL_advsimd_vec(context *ctx, Instruction *instr) |
no test coverage detected