fminv_advsimd.xml */
| 8713 | |
| 8714 | /* fminv_advsimd.xml */ |
| 8715 | int FMINV_advsimd(context *ctx, Instruction *instr) |
| 8716 | { |
| 8717 | int rc = DECODE_STATUS_UNMATCHED; |
| 8718 | /* class iclass_half */ |
| 8719 | /* 0|Q=x|U=0|01110|o1=1|0|11000|opcode=01111|10|Rn=xxxxx|Rd=xxxxx */ |
| 8720 | if((INSWORD & 0xBFFFFC00)==0xEB0F800) { |
| 8721 | decode_fields32(ENC_FMINV_ASIMDALL_ONLY_H, ctx, instr); |
| 8722 | if(!HaveFP16Ext()) { |
| 8723 | UNDEFINED; |
| 8724 | } |
| 8725 | ctx->d = UINT(ctx->Rd); |
| 8726 | ctx->n = UINT(ctx->Rn); |
| 8727 | ctx->esize = 0x10; |
| 8728 | ctx->datasize = (ctx->Q==1) ? 0x80 : 0x40; |
| 8729 | ctx->elements = ((ctx->esize) ? ((ctx->datasize) / (ctx->esize)) : 0); |
| 8730 | ctx->op = (ctx->o1==1) ? ReduceOp_FMIN : ReduceOp_FMAX; |
| 8731 | OK(ENC_FMINV_ASIMDALL_ONLY_H); |
| 8732 | } |
| 8733 | /* class iclass_single_and_double */ |
| 8734 | /* 0|Q=x|U=1|01110|o1=1|sz=x|11000|opcode=01111|10|Rn=xxxxx|Rd=xxxxx */ |
| 8735 | if((INSWORD & 0xBFBFFC00)==0x2EB0F800) { |
| 8736 | decode_fields32(ENC_FMINV_ASIMDALL_ONLY_SD, ctx, instr); |
| 8737 | ctx->d = UINT(ctx->Rd); |
| 8738 | ctx->n = UINT(ctx->Rn); |
| 8739 | if(((ctx->sz<<1)|ctx->Q)!=1) { |
| 8740 | UNDEFINED; |
| 8741 | } |
| 8742 | ctx->esize = (0x20) << (UINT(ctx->sz)); |
| 8743 | ctx->datasize = (ctx->Q==1) ? 0x80 : 0x40; |
| 8744 | ctx->elements = ((ctx->esize) ? ((ctx->datasize) / (ctx->esize)) : 0); |
| 8745 | ctx->op = (ctx->o1==1) ? ReduceOp_FMIN : ReduceOp_FMAX; |
| 8746 | OK(ENC_FMINV_ASIMDALL_ONLY_SD); |
| 8747 | } |
| 8748 | return rc; |
| 8749 | } |
| 8750 | |
| 8751 | /* fmin_advsimd.xml */ |
| 8752 | int FMIN_advsimd(context *ctx, Instruction *instr) |
no test coverage detected