fminnmp_advsimd_vec.xml */
| 8469 | |
| 8470 | /* fminnmp_advsimd_vec.xml */ |
| 8471 | int FMINNMP_advsimd_vec(context *ctx, Instruction *instr) |
| 8472 | { |
| 8473 | int rc = DECODE_STATUS_UNMATCHED; |
| 8474 | /* class iclass_half */ |
| 8475 | /* 0|Q=x|U=1|01110|a=1|10|Rm=xxxxx|00|Op3=000|1|Rn=xxxxx|Rd=xxxxx */ |
| 8476 | if((INSWORD & 0xBFE0FC00)==0x2EC00400) { |
| 8477 | decode_fields32(ENC_FMINNMP_ASIMDSAMEFP16_ONLY, ctx, instr); |
| 8478 | if(!HaveFP16Ext()) { |
| 8479 | UNDEFINED; |
| 8480 | } |
| 8481 | ctx->d = UINT(ctx->Rd); |
| 8482 | ctx->n = UINT(ctx->Rn); |
| 8483 | ctx->m = UINT(ctx->Rm); |
| 8484 | ctx->esize = 0x10; |
| 8485 | ctx->datasize = (ctx->Q==1) ? 0x80 : 0x40; |
| 8486 | ctx->elements = ((ctx->esize) ? ((ctx->datasize) / (ctx->esize)) : 0); |
| 8487 | ctx->pair = (ctx->U==1); |
| 8488 | ctx->minimum = (ctx->a==1); |
| 8489 | OK(ENC_FMINNMP_ASIMDSAMEFP16_ONLY); |
| 8490 | } |
| 8491 | /* class iclass_single_and_double */ |
| 8492 | /* 0|Q=x|U=1|01110|o1=1|sz=x|1|Rm=xxxxx|opcode=11000|1|Rn=xxxxx|Rd=xxxxx */ |
| 8493 | if((INSWORD & 0xBFA0FC00)==0x2EA0C400) { |
| 8494 | decode_fields32(ENC_FMINNMP_ASIMDSAME_ONLY, ctx, instr); |
| 8495 | ctx->d = UINT(ctx->Rd); |
| 8496 | ctx->n = UINT(ctx->Rn); |
| 8497 | ctx->m = UINT(ctx->Rm); |
| 8498 | if(((ctx->sz<<1)|ctx->Q)==2) { |
| 8499 | UNDEFINED; |
| 8500 | } |
| 8501 | ctx->esize = (0x20) << (UINT(ctx->sz)); |
| 8502 | ctx->datasize = (ctx->Q==1) ? 0x80 : 0x40; |
| 8503 | ctx->elements = ((ctx->esize) ? ((ctx->datasize) / (ctx->esize)) : 0); |
| 8504 | ctx->pair = (ctx->U==1); |
| 8505 | ctx->minimum = (ctx->o1==1); |
| 8506 | OK(ENC_FMINNMP_ASIMDSAME_ONLY); |
| 8507 | } |
| 8508 | return rc; |
| 8509 | } |
| 8510 | |
| 8511 | /* fminnmv_advsimd.xml */ |
| 8512 | int FMINNMV_advsimd(context *ctx, Instruction *instr) |
no test coverage detected