fmaxv_advsimd.xml */
| 8307 | |
| 8308 | /* fmaxv_advsimd.xml */ |
| 8309 | int FMAXV_advsimd(context *ctx, Instruction *instr) |
| 8310 | { |
| 8311 | int rc = DECODE_STATUS_UNMATCHED; |
| 8312 | /* class iclass_half */ |
| 8313 | /* 0|Q=x|U=0|01110|o1=0|0|11000|opcode=01111|10|Rn=xxxxx|Rd=xxxxx */ |
| 8314 | if((INSWORD & 0xBFFFFC00)==0xE30F800) { |
| 8315 | decode_fields32(ENC_FMAXV_ASIMDALL_ONLY_H, ctx, instr); |
| 8316 | if(!HaveFP16Ext()) { |
| 8317 | UNDEFINED; |
| 8318 | } |
| 8319 | ctx->d = UINT(ctx->Rd); |
| 8320 | ctx->n = UINT(ctx->Rn); |
| 8321 | ctx->esize = 0x10; |
| 8322 | ctx->datasize = (ctx->Q==1) ? 0x80 : 0x40; |
| 8323 | ctx->elements = ((ctx->esize) ? ((ctx->datasize) / (ctx->esize)) : 0); |
| 8324 | ctx->op = (ctx->o1==1) ? ReduceOp_FMIN : ReduceOp_FMAX; |
| 8325 | OK(ENC_FMAXV_ASIMDALL_ONLY_H); |
| 8326 | } |
| 8327 | /* class iclass_single_and_double */ |
| 8328 | /* 0|Q=x|U=1|01110|o1=0|sz=x|11000|opcode=01111|10|Rn=xxxxx|Rd=xxxxx */ |
| 8329 | if((INSWORD & 0xBFBFFC00)==0x2E30F800) { |
| 8330 | decode_fields32(ENC_FMAXV_ASIMDALL_ONLY_SD, ctx, instr); |
| 8331 | ctx->d = UINT(ctx->Rd); |
| 8332 | ctx->n = UINT(ctx->Rn); |
| 8333 | if(((ctx->sz<<1)|ctx->Q)!=1) { |
| 8334 | UNDEFINED; |
| 8335 | } |
| 8336 | ctx->esize = (0x20) << (UINT(ctx->sz)); |
| 8337 | ctx->datasize = (ctx->Q==1) ? 0x80 : 0x40; |
| 8338 | ctx->elements = ((ctx->esize) ? ((ctx->datasize) / (ctx->esize)) : 0); |
| 8339 | ctx->op = (ctx->o1==1) ? ReduceOp_FMIN : ReduceOp_FMAX; |
| 8340 | OK(ENC_FMAXV_ASIMDALL_ONLY_SD); |
| 8341 | } |
| 8342 | return rc; |
| 8343 | } |
| 8344 | |
| 8345 | /* fmax_advsimd.xml */ |
| 8346 | int FMAX_advsimd(context *ctx, Instruction *instr) |
no test coverage detected