Function FCVTZU_float_int

arch/arm64/disassembler/decode2.c:7704–7787

fcvtzu_float_int.xml */

/* fcvtzu_float_int.xml */
int FCVTZU_float_int(context *ctx, Instruction *instr)
{
	int rc = DECODE_STATUS_UNMATCHED;
	/* class iclass_float */
	/* sf=x|0|S=0|11110|ftype=xx|1|rmode=11|opcode=001|000000|Rn=xxxxx|Rd=xxxxx */
	if((INSWORD & 0x7F3FFC00)==0x1E390000) {
		decode_fields32(ENC_FCVTZU_32H_FLOAT2INT, ctx, instr);
		ctx->d = UINT(ctx->Rd);
		ctx->n = UINT(ctx->Rn);
		ctx->intsize = (ctx->sf==1) ? 0x40 : 0x20;
		if(!ctx->ftype) {
			ctx->fltsize = 0x20;
		}
		else if(ctx->ftype==1) {
			ctx->fltsize = 0x40;
		}
		else if(ctx->ftype==2) {
			if(((SLICE(ctx->opcode,2,1)<<2)|ctx->rmode)!=13) {
				UNDEFINED;
			}
			ctx->fltsize = 0x80;
		}
		else if(ctx->ftype==3) {
			if(HaveFP16Ext()) {
				ctx->fltsize = 0x10;
			}
			else {
				UNDEFINED;
			}
		}
		if(!(((SLICE(ctx->opcode,2,1)<<2)|ctx->rmode)&12)) {
			ctx->rounding = FPDecodeRounding(ctx->rmode);
			ctx->unsigned_ = (SLICE(ctx->opcode,0,0)==1);
			ctx->op = FPConvOp_CVT_FtoI;
		}
		else if(((SLICE(ctx->opcode,2,1)<<2)|ctx->rmode)==4) {
			ctx->rounding = FPRoundingMode(ctx->FPCR);
			ctx->unsigned_ = (SLICE(ctx->opcode,0,0)==1);
			ctx->op = FPConvOp_CVT_ItoF;
		}
		else if(((SLICE(ctx->opcode,2,1)<<2)|ctx->rmode)==8) {
			ctx->rounding = FPRounding_TIEAWAY;
			ctx->unsigned_ = (SLICE(ctx->opcode,0,0)==1);
			ctx->op = FPConvOp_CVT_FtoI;
		}
		else if(((SLICE(ctx->opcode,2,1)<<2)|ctx->rmode)==12) {
			if(ctx->fltsize!=0x10 && ctx->fltsize!=ctx->intsize) {
				UNDEFINED;
			}
			if(SLICE(ctx->opcode,0,0)==1) {
				ctx->op = FPConvOp_MOV_ItoF;
			};
			ctx->part = 0;
		}
		else if(((SLICE(ctx->opcode,2,1)<<2)|ctx->rmode)==13) {
			if(ctx->intsize!=0x40 || ctx->fltsize!=0x80) {
				UNDEFINED;
			}