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Macro: Set the rounding mode bits of the MXCSR control and status register to the value in unsigned 32-bit integer a. The rounding mode may contain an

Compute the bitwise AND of 128 bits (representing integer data) in a and b, and store the result in dst. https://www.intel.com/content/www/us/en/docs/

Compute the bitwise NOT of packed double-precision (64-bit) floating-point elements in a and then AND with b, and store the results in dst. https://ww

Compare packed double-precision (64-bit) floating-point elements in a and b for equality, and store the results in dst. https://www.intel.com/content/

Compare packed single-precision (32-bit) floating-point elements in a and b for equality, and store the results in dst. https://www.intel.com/content/

Compare packed double-precision (64-bit) floating-point elements in a and b for greater-than-or-equal, and store the results in dst. https://www.intel

Compare packed double-precision (64-bit) floating-point elements in a and b for greater-than, and store the results in dst. https://www.intel.com/cont

Compare packed double-precision (64-bit) floating-point elements in a and b for less-than-or-equal, and store the results in dst. https://www.intel.co

Compare packed signed 16-bit integers in a and b for less-than, and store the results in dst. Note: This intrinsic emits the pcmpgtw instruction with

Compare packed signed 32-bit integers in a and b for less-than, and store the results in dst. Note: This intrinsic emits the pcmpgtd instruction with

Compare packed double-precision (64-bit) floating-point elements in a and b for less-than, and store the results in dst. https://www.intel.com/content

Compare packed single-precision (32-bit) floating-point elements in a and b for less-than, and store the results in dst. https://www.intel.com/content

Compare packed double-precision (64-bit) floating-point elements in a and b for not-equal, and store the results in dst. https://www.intel.com/content

Compare packed single-precision (32-bit) floating-point elements in a and b for not-equal, and store the results in dst. https://www.intel.com/content

Compare packed double-precision (64-bit) floating-point elements in a and b for not-greater-than-or-equal, and store the results in dst. https://www.i

Compare packed single-precision (32-bit) floating-point elements in a and b for not-greater-than-or-equal, and store the results in dst. https://www.i

Compare packed double-precision (64-bit) floating-point elements in a and b for not-greater-than, and store the results in dst. https://www.intel.com/

Compare packed single-precision (32-bit) floating-point elements in a and b for not-greater-than, and store the results in dst. https://www.intel.com/

Compare packed double-precision (64-bit) floating-point elements in a and b for not-less-than-or-equal, and store the results in dst. https://www.inte

Compare packed single-precision (32-bit) floating-point elements in a and b for not-less-than-or-equal, and store the results in dst. https://www.inte

Compare packed double-precision (64-bit) floating-point elements in a and b for not-less-than, and store the results in dst. https://www.intel.com/con

Compare packed single-precision (32-bit) floating-point elements in a and b for not-less-than, and store the results in dst. https://www.intel.com/con

Compare packed double-precision (64-bit) floating-point elements in a and b to see if neither is NaN, and store the results in dst. https://www.intel.

Compare packed single-precision (32-bit) floating-point elements in a and b to see if neither is NaN, and store the results in dst. https://www.intel.

Compare packed double-precision (64-bit) floating-point elements in a and b to see if either is NaN, and store the results in dst. https://www.intel.c

Compare packed single-precision (32-bit) floating-point elements in a and b to see if either is NaN, and store the results in dst. https://www.intel.c

Compare the lower double-precision (64-bit) floating-point element in a and b for equality, and return the boolean result (0 or 1). https://www.intel.

Compare the lower single-precision (32-bit) floating-point element in a and b for equality, and return the boolean result (0 or 1). https://www.intel.

Convert packed single-precision (32-bit) floating-point elements in a to packed 16-bit integers, and store the results in dst. Note: this intrinsic wi

Convert packed single-precision (32-bit) floating-point elements in a to packed 32-bit integers with truncation, and store the results in dst. https:/

Divide packed double-precision (64-bit) floating-point elements in a by packed elements in b, and store the results in dst. https://www.intel.com/cont

Get the unsigned 32-bit value of the MXCSR control and status register. https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=

Load a double-precision (64-bit) floating-point element from memory into both elements of dst. https://www.intel.com/content/www/us/en/docs/intrinsics

Loads two double-precision from unaligned memory, floating-point values. https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text

Load 128-bits of integer data from memory into dst. mem_addr does not need to be aligned on any particular boundary. https://www.intel.com/content/www

Compare the lower double-precision (64-bit) floating-point elements in a and b, store the maximum value in the lower element of dst, and copy the uppe

Compare the lower double-precision (64-bit) floating-point elements in a and b, store the minimum value in the lower element of dst, and copy the uppe

Compute the bitwise OR of packed double-precision (64-bit) floating-point elements in a and b, and store the results in dst. https://www.intel.com/con

Compute the approximate reciprocal of the lower single-precision (32-bit) floating-point element in a, store the result in the lower element of dst, a

Broadcast 32-bit integer a to all elements of dst. https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_set1_epi32

Broadcast single-precision (32-bit) floating-point value a to all elements of dst. https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index

Set the MXCSR control and status register with the value in unsigned 32-bit integer a. https://www.intel.com/content/www/us/en/docs/intrinsics-guide/i

Set packed single-precision (32-bit) floating-point elements in dst with the supplied values in reverse order. https://www.intel.com/content/www/us/en

Return vector of type __m128d with all elements set to zero. https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_setzero

Compute the square root of packed double-precision (64-bit) floating-point elements in a, and store the results in dst. https://www.intel.com/content/

Compute the square root of packed single-precision (32-bit) floating-point elements in a, and store the results in dst. Due to ARMv7-A NEON's lack of

Store 128-bits (composed of 4 packed single-precision (32-bit) floating-point elements) from a into memory. mem_addr must be aligned on a 16-byte boun

Store 128-bits (composed of 2 packed double-precision (64-bit) floating-point elements) from a into memory. mem_addr does not need to be aligned on an

Subtract packed 32-bit integers in b from packed 32-bit integers in a, and store the results in dst. https://www.intel.com/content/www/us/en/docs/intr

Compute the bitwise XOR of packed double-precision (64-bit) floating-point elements in a and b, and store the results in dst. https://www.intel.com/co

Compute the bitwise XOR of packed single-precision (32-bit) floating-point elements in a and b, and store the results in dst. https://www.intel.com/co

emulate vaddvq u8 variant */

bipolarToUnipolar() calculates the unipolar (0 -> 1) value from a bipolar (-1 -> +1) value dValue = the value to convert */

calcInverseValueVoltOctaveExp() returns a value between 0 -> 1 representing the volt/octave control location dLowLimit = low limit of control dHighL

[MiscUserCode] You can add your own definitions of your custom methods or any other code here...