| 6674 | } |
| 6675 | |
| 6676 | FP16 float_to_half_full(FP32 f) { |
| 6677 | FP16 o = {0}; |
| 6678 | |
| 6679 | // Based on ISPC reference code (with minor modifications) |
| 6680 | if (f.s.Exponent == 0) // Signed zero/denormal (which will underflow) |
| 6681 | o.s.Exponent = 0; |
| 6682 | else if (f.s.Exponent == 255) // Inf or NaN (all exponent bits set) |
| 6683 | { |
| 6684 | o.s.Exponent = 31; |
| 6685 | o.s.Mantissa = f.s.Mantissa ? 0x200 : 0; // NaN->qNaN and Inf->Inf |
| 6686 | } else // Normalized number |
| 6687 | { |
| 6688 | // Exponent unbias the single, then bias the halfp |
| 6689 | int newexp = f.s.Exponent - 127 + 15; |
| 6690 | if (newexp >= 31) // Overflow, return signed infinity |
| 6691 | o.s.Exponent = 31; |
| 6692 | else if (newexp <= 0) // Underflow |
| 6693 | { |
| 6694 | if ((14 - newexp) <= 24) // Mantissa might be non-zero |
| 6695 | { |
| 6696 | unsigned int mant = f.s.Mantissa | 0x800000; // Hidden 1 bit |
| 6697 | o.s.Mantissa = mant >> (14 - newexp); |
| 6698 | if ((mant >> (13 - newexp)) & 1) // Check for rounding |
| 6699 | o.u++; // Round, might overflow into exp bit, but this is OK |
| 6700 | } |
| 6701 | } else { |
| 6702 | o.s.Exponent = newexp; |
| 6703 | o.s.Mantissa = f.s.Mantissa >> 13; |
| 6704 | if (f.s.Mantissa & 0x1000) // Check for rounding |
| 6705 | o.u++; // Round, might overflow to inf, this is OK |
| 6706 | } |
| 6707 | } |
| 6708 | |
| 6709 | o.s.Sign = f.s.Sign; |
| 6710 | return o; |
| 6711 | } |
| 6712 | |
| 6713 | // NOTE: From OpenEXR code |
| 6714 | // #define IMF_INCREASING_Y 0 |
no outgoing calls
no test coverage detected